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公开(公告)号:US09680422B2
公开(公告)日:2017-06-13
申请号:US14154022
申请日:2014-01-13
Applicant: QUALCOMM Incorporated
Inventor: Qijia Liu , Jifeng Geng , Daniel Fred Filipovic , Li Gao
CPC classification number: H03F1/3241 , H03F1/30 , H03F1/3247 , H03F3/195 , H03F3/245 , H03F2200/111 , H03F2200/336 , H03F2200/447 , H03F2201/3233 , H04L27/368
Abstract: Exemplary embodiments are related to power amplifier power level compensation in a pre-distortion system. A method may include applying digital pre-distortion (DPD) of a power amplifier at a frequency channel, a fixed input power value, and a fixed temperature. The method may also include determining an optimal input power value for the power amplifier in response to a change in at least one of frequency and temperature.
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公开(公告)号:US20170325101A1
公开(公告)日:2017-11-09
申请号:US15148629
申请日:2016-05-06
Applicant: QUALCOMM Incorporated
Inventor: Joseph Gates , Li Gao , Narendra Gottimukkala , Douglas Grover , Insung Kang , Dongbo Zhang
CPC classification number: H04L25/03019 , H04B1/0007 , H04L25/03343 , H04W24/06
Abstract: Embodiments described herein provide a method and apparatus for monitoring and correcting a transmit signal. A first sample is taken before the signal is input to a digital to analog converter (DAC) in a transmit chain. A second sample is taken of the transmit signal after the signal has passed through the power amplifier (PA). The first and second transmit samples are then compared and an equalizer interpolation value is determined. This equalizer interpolation value is applied to the transmit signal before transmission to provide a transmit signal with improved quality. The apparatus includes a feedback receive correction unit; a time domain processor in communication with the feedback receive correction unit; a frequency domain processing equalizer in communication with the time domain processor; an equalizer interpolation unit; an absolute value squaring unit in communication with the equalizer interpolation unit; and a processor for computation of a transmit quality parameter.
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公开(公告)号:US20160080119A1
公开(公告)日:2016-03-17
申请号:US14484523
申请日:2014-09-12
Applicant: QUALCOMM Incorporated
Inventor: Rema Vaidyanathan , Prasad Srinivasa Siva Gudem , Vijay Chellappa , Chalin Chac Lee , Li Gao , David Coronel
CPC classification number: H04L1/206 , H03L7/06 , H04B3/46 , H04B17/102
Abstract: A method and apparatus for self-testing a GSM/EDGE communications device. An embodiment provides a method of measuring transmit power. A receive phase locked loop (PLL) is inserted into a feedback receiver local oscillator mixer. The receive PLL is then tuned to a local oscillator frequency. Once the tuning is complete, an I and a Q signal are captured using a channel of the feedback receiver. After capture, a I2+Q2 sum is computed, measuring the transmit power. The feedback receiver automatic gain control (AGC) may be used to determine transmit power in place of I2+Q2. The apparatus includes: a modem assembly, a power control assembly, a power amplifier, a duplexer, a coupler and a switch. The power control assembly further includes a first PLL and first and second mixers. The second mixer is connected to a feedback low noise amplifier and receives input from a feedback receiver PLL.
Abstract translation: 一种用于自测试GSM / EDGE通信设备的方法和装置。 实施例提供了一种测量发射功率的方法。 接收锁相环(PLL)插入到反馈接收机本地振荡器混频器中。 然后将接收PLL调谐到本地振荡器频率。 调谐完成后,使用反馈接收器的通道捕获I和Q信号。 捕获后,计算I2 + Q2和,测量发射功率。 反馈接收机自动增益控制(AGC)可用于确定发射功率代替I2 + Q2。 该装置包括:调制解调器组件,功率控制组件,功率放大器,双工器,耦合器和开关。 功率控制组件还包括第一PLL和第一和第二混频器。 第二混频器连接到反馈低噪声放大器,并从反馈接收机PLL接收输入。
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公开(公告)号:US20180124716A1
公开(公告)日:2018-05-03
申请号:US15472943
申请日:2017-03-29
Applicant: QUALCOMM Incorporated
Inventor: Sudarsan Krishnan , Andrei Izotov , Carl Hardin , Vijay Chellappa , Li Gao
IPC: H04W52/52
CPC classification number: H04W52/52 , H03F1/00 , H03F1/0272 , H03F1/3247 , H03F3/19 , H03F3/245 , H03F2200/451 , H04L49/109 , H04Q2213/13199
Abstract: A radio frequency (RF) system including: a modem configured to generate a first set of digital bits and to create an analog RF signal from those digital bits; a power amplifier configured to receive the analog RF signal and to amplify the analog RF signal, the power amplifier including an input for a biasing voltage; a feedback loop configured to sample an output of the power amplifier, generate a second set of digital bits corresponding to the first set of digital bits, digitally process the second set of digital bits to determine a linearity characteristic of the power amplifier, and to adjust the biasing voltage in response to determining the linearity characteristic.
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