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公开(公告)号：US10558393B2
公开(公告)日：2020-02-11
申请号：US15789903
申请日：2017-10-20
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , David Teb , Hung Vuong
Abstract: A system is proposed to enable a hardware based host controller to perform operations related to Host-aware Performance booster (HPB). The host controller may retrieve a command packet from a host memory targeting a logical address of a storage location of the storage device, may retrieve a physical address of the storage device mapped to the logical address from the address map, and may send the command packet to the storage device. The sent command packet may have the physical address incorporated therein.
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公开(公告)号：US10510382B2
公开(公告)日：2019-12-17
申请号：US15782833
申请日：2017-10-12
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , David Teb , Hung Vuong , Venkatakrishnan Gopalakrishnan
Abstract: In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.
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公开(公告)号：US10444999B2
公开(公告)日：2019-10-15
申请号：US15292675
申请日：2016-10-13
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , David Teb , Hung Vuong
Abstract: Systems and method are directed to a Universal Flash Storage (UFS) host capable of interfacing one or more UFS devices. The UFS host includes a plurality of mobile-physical-layers (M-PHYs) for supporting one or more lanes of traffic between the UFS host and the one or more UFS devices. A Reference M-PHY MODULE Interface (RMMI) router is coupled between a Unified Protocol link layer (Unipro) and the plurality of M-PHYs. The RMMI router is configurable in a transparent mode to pass traffic, without routing, between the UFS host and a 2-lane embedded UFS device through the two M-PHYs. The RMMI router is configurable in a routing mode, to route traffic to a first M-PHY interfacing a 1-lane embedded UFS device or to a second M-PHY interfacing a 1-lane removable UFS card. The RMMI router is configurable based on metal strap or read only memory (ROM) setting.
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公开(公告)号：US09690720B2
公开(公告)日：2017-06-27
申请号：US14728400
申请日：2015-06-02
Applicant: QUALCOMM Incorporated
Inventor： Assaf Shacham , Maya Haim , Lee Susman , David Teb
CPC classification number: G06F13/1642 , G06F3/06 , G06F3/061 , G06F3/0664 , G06F3/0688 , G06F13/16
Abstract: Command trapping in an input/output virtualization (IOV) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is configured to receive a request from a client register interface (CRI) of one of multiple input/output (I/O) clients. The IOV-HC inspects a content of the request prior to the request being passed to a transport protocol engine. Based on the content, the IOV-HC determines whether the request should be further processed or should be trapped. If the IOV-HC determines that the request should be trapped, the IOV-HC traps the request using a request trap. In some aspects, the IOV-HC generates an interrupt to a virtual machine manager (VMM) to notify the VMM that the request was trapped. In some aspects, the IOV-HC provides a response generation circuit to receive instructions from the VMM to generate a response to the CRI from which the trapped request originated.
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公开(公告)号：US12248422B2
公开(公告)日：2025-03-11
申请号：US18314359
申请日：2023-05-09
Applicant: QUALCOMM Incorporated
Inventor： Tomer Rafael Ben-Chen , Yaron Shachar , David Teb
Abstract: Systems and method for lane management in a communication bus are disclosed. In one aspects, a communication link or bus between a baseband processor (BBP) and a radio frequency integrated circuit (RFIC) may include multiple uplink lanes for transmission and multiple downlink lanes for reception that are frequency constrained and adjust bandwidth by adjusting duty cycles on the lanes. To reduce power consumption by the communication bus, exemplary aspects of the present disclosure contemplate using in-band signaling to turn off lanes selectively during inactive periods such that the lanes do not duty cycle in tandem with active lanes. Additionally, in some aspects, the uplink lanes may be continuously active during transmission while the downlink lanes are turned off. This dynamic lane usage reduces power consumption, does not require additional pins for sideband signaling, and does not introduce any additional latency.
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Patent Agency Ranking
公开(公告)号：US20240378164A1
公开(公告)日：2024-11-14
申请号：US18314359
申请日：2023-05-09
Applicant: QUALCOMM Incorporated
Inventor： Tomer Rafael Ben-Chen , Yaron Shachar , David Teb
Abstract: Systems and method for lane management in a communication bus are disclosed. In one aspects, a communication link or bus between a baseband processor (BBP) and a radio frequency integrated circuit (RFIC) may include multiple uplink lanes for transmission and multiple downlink lanes for reception that are frequency constrained and adjust bandwidth by adjusting duty cycles on the lanes. To reduce power consumption by the communication bus, exemplary aspects of the present disclosure contemplate using in-band signaling to turn off lanes selectively during inactive periods such that the lanes do not duty cycle in tandem with active lanes. Additionally, in some aspects, the uplink lanes may be continuously active during transmission while the downlink lanes are turned off. This dynamic lane usage reduces power consumption, does not require additional pins for sideband signaling, and does not introduce any additional latency.
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公开(公告)号：US09881680B2
公开(公告)日：2018-01-30
申请号：US14728296
申请日：2015-06-02
Applicant: QUALCOMM Incorporated
Inventor： Assaf Shacham , Lee Susman , David Teb
CPC classification number: G11C16/30 , G06F1/266 , G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F13/1663
Abstract: A multi-host power controller (MHPC) of a flash-memory-based storage device is disclosed. In one aspect, the MHPC receives power mode change requests from each of multiple input/output (I/O) clients. The MHPC extracts and stores a “vote,” or a requested power mode, from the power mode change requests, and then applies a voting logic to the stored votes to determine whether to transition the flash-memory-based storage device between power modes. If the flash-memory-based storage device is not currently operating in the power mode determined by the MHPC, the MHPC is configured to issue a power mode change command to the flash-memory-based storage device to transition to the determined power mode. In this manner, the MHPC is able to control the power mode of the flash-memory-based storage device while receiving direct power mode change requests from multiple I/O clients.
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公开(公告)号：US20170269956A1
公开(公告)日：2017-09-21
申请号：US15075945
申请日：2016-03-21
Applicant: QUALCOMM Incorporated
Inventor： Assaf Shacham , Tom Yahalom , David Teb
CPC classification number: G06F9/45558 , G06F3/0605 , G06F3/0613 , G06F3/062 , G06F3/0635 , G06F3/0644 , G06F3/0659 , G06F3/0664 , G06F3/067 , G06F3/0679 , G06F2009/45583 , G06F2009/45595
Abstract: Storage resource management in virtualized environments is provided. In this regard, when receiving a request for accessing a target general purpose partition (GPP) in a storage device, partition switching circuitry is configured to determine whether the target GPP equals a current GPP that is accessed by a list of existing requests. The partition switching circuitry adds the request into the list of existing requests if the target GPP equals the current GPP. Otherwise, the partition switching circuitry waits for the list of existing requests to be executed on the current GPP before switching to the target GPP to execute the request received from a client. By switching to the target GPP after executing the list of existing commands on the current GPP, it is possible to share a plurality of GPPs among multiple clients in a virtualized environment while maintaining data integrity and security in the storage device.
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公开(公告)号：US09891945B2
公开(公告)日：2018-02-13
申请号：US15075945
申请日：2016-03-21
Applicant: QUALCOMM Incorporated
Inventor： Assaf Shacham , Tom Yahalom , David Teb
CPC classification number: G06F9/45558 , G06F3/0605 , G06F3/0613 , G06F3/062 , G06F3/0635 , G06F3/0644 , G06F3/0659 , G06F3/0664 , G06F3/067 , G06F3/0679 , G06F2009/45583 , G06F2009/45595
Abstract: Storage resource management in virtualized environments is provided. In this regard, when receiving a request for accessing a target general purpose partition (GPP) in a storage device, partition switching circuitry is configured to determine whether the target GPP equals a current GPP that is accessed by a list of existing requests. The partition switching circuitry adds the request into the list of existing requests if the target GPP equals the current GPP. Otherwise, the partition switching circuitry waits for the list of existing requests to be executed on the current GPP before switching to the target GPP to execute the request received from a client. By switching to the target GPP after executing the list of existing commands on the current GPP, it is possible to share a plurality of GPPs among multiple clients in a virtualized environment while maintaining data integrity and security in the storage device.
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公开(公告)号：US09542340B2
公开(公告)日：2017-01-10
申请号：US14728343
申请日：2015-06-02
Applicant: QUALCOMM Incorporated
Inventor： Assaf Shacham , Dolev Raviv , David Teb
Abstract: An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.
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