公开(公告)号：US09690720B2

公开(公告)日：2017-06-27

申请号：US14728400

申请日：2015-06-02

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Maya Haim ,  Lee Susman ,  David Teb

IPC: G06F12/00 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F13/1642 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0688 ,  G06F13/16

Abstract: Command trapping in an input/output virtualization (IOV) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is configured to receive a request from a client register interface (CRI) of one of multiple input/output (I/O) clients. The IOV-HC inspects a content of the request prior to the request being passed to a transport protocol engine. Based on the content, the IOV-HC determines whether the request should be further processed or should be trapped. If the IOV-HC determines that the request should be trapped, the IOV-HC traps the request using a request trap. In some aspects, the IOV-HC generates an interrupt to a virtual machine manager (VMM) to notify the VMM that the request was trapped. In some aspects, the IOV-HC provides a response generation circuit to receive instructions from the VMM to generate a response to the CRI from which the trapped request originated.

公开(公告)号：US20150074338A1

公开(公告)日：2015-03-12

申请号：US14467404

申请日：2014-08-25

Applicant: QUALCOMM Incorporated

Inventor： Dolev Raviv ,  Tatyana Brokhman ,  Maya Haim ,  Assaf Shacham

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G06F13/385 ,  G06F2206/1014

Abstract: Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.

Abstract translation: 公开闪存中的确定命令完成。 示例性方面包括消除软件锁定和未完成的请求变量并用传送请求完成寄存器替换它们。 转移请求完成寄存器可以映射到通用闪存存储（UFS）传输协议（UTP）传输请求列表（UTRL）槽。 主机的控制器 - 硬件组件 - 可以在转移请求完成时将门铃寄存器清零的同时设置在传送请求完成寄存器中的位。 读取该位后，转移请求完成寄存器中的位将被清零。

公开(公告)号：US09442793B2

公开(公告)日：2016-09-13

申请号：US14338279

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Itai Lanel ,  Maya Haim

IPC: G06F11/07 ,  G06F11/30 ,  G06F11/34 ,  G06F13/00

CPC classification number: G06F11/0793 ,  G06F11/0721 ,  G06F11/0745 ,  G06F11/0772 ,  G06F11/3024 ,  G06F11/3409 ,  G06F13/00 ,  G06F2201/86

Abstract: A method for error detection and recovery is provided in which a host controller and host software collaborate together. The host controller may: detect an error condition, set an error interrupt or register, and/or halt task execution or processing at the host controller. The host software may: detect an error condition as a result of the host controller having set the error interrupt or register; performs error handling, and clears the error condition. The host controller then resumes execution or processing of tasks upon detecting that error condition has been cleared by the host software.

Abstract translation: 提供了一种用于错误检测和恢复的方法，其中主机控制器和主机软件协同工作。 主机控制器可以：在主机控制器处检测错误状况，设置错误中断或寄存器，和/或停止任务执行或处理。 主机软件可以：由主机控制器设置错误中断或寄存器的结果来检测错误状况; 执行错误处理，并清除错误条件。 主机控制器在检测到主机软件已经清除了错误状况后，继续执行或处理任务。

公开(公告)号：US09348537B2

公开(公告)日：2016-05-24

申请号：US14467404

申请日：2014-08-25

Applicant: QUALCOMM Incorporated

Inventor： Dolev Raviv ,  Tatyana Brokhman ,  Maya Haim ,  Assaf Shacham

IPC: G06F3/06 ,  G06F13/38

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G06F13/385 ,  G06F2206/1014

Abstract: Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.

Abstract translation: 公开闪存中的确定命令完成。 示例性方面包括消除软件锁定和未完成的请求变量并用传送请求完成寄存器替换它们。 转移请求完成寄存器可以映射到通用闪存存储（UFS）传输协议（UTP）传输请求列表（UTRL）槽。 主机的控制器 - 硬件组件 - 可以在转移请求完成时将门铃寄存器清零的同时设置在传送请求完成寄存器中的位。 读取该位后，转移请求完成寄存器中的位将被清零。

公开(公告)号：US20150347017A1

公开(公告)日：2015-12-03

申请号：US14728400

申请日：2015-06-02

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Maya Haim ,  Lee Susman ,  David Teb

IPC: G06F3/06

CPC classification number: G06F13/1642 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0688 ,  G06F13/16

Abstract: Command trapping in an input/output virtualization (IOV) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is configured to receive a request from a client register interface (CRI) of one of multiple input/output (I/O) clients. The IOV-HC inspects a content of the request prior to the request being passed to a transport protocol engine. Based on the content, the IOV-HC determines whether the request should be further processed or should be trapped. If the IOV-HC determines that the request should be trapped, the IOV-HC traps the request using a request trap. In some aspects, the IOV-HC generates an interrupt to a virtual machine manager (VMM) to notify the VMM that the request was trapped. In some aspects, the IOV-HC provides a response generation circuit to receive instructions from the VMM to generate a response to the CRI from which the trapped request originated.

Abstract translation: 公开了基于闪存存储器的存储设备的输入/输出虚拟化（IOV）主机控制器（HC）（IOV-HC）中的命令捕获。 在一个方面，IOV-HC被配置为从多个输入/输出（I / O）客户端之一的客户端寄存器接口（CRI）接收请求。 在请求被传递到传输协议引擎之前，IOV-HC检查请求的内容。 根据内容，IOV-HC确定请求是否应进一步处理或应被捕获。 如果IOV-HC确定请求被捕获，则IOV-HC使用请求陷阱捕获请求。 在某些方面，IOV-HC会向虚拟机管理器（VMM）产生中断，以通知VMM该请求被捕获。 在一些方面，IOV-HC提供响应生成电路以从VMM接收指令以产生对被捕获请求产生的CRI的响应。