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公开(公告)号：US20230394738A1
公开(公告)日：2023-12-07
申请号：US18035507
申请日：2020-11-09
Applicant: QUALCOMM Incorporated
Inventor： Yibin ZHANG , Zilin YING , Yun DU , Heng QI , Jiexia YU , Yang YU , Andrew Evan GRUBER , Jian LIANG , Tao WANG , Alexei Vladimirovich BOURD , Gang ZHONG , Minjie HUANG
IPC: G06T15/00
CPC classification number: G06T15/005
Abstract: The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.
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公开(公告)号：US20240296153A1
公开(公告)日：2024-09-05
申请号：US18177390
申请日：2023-03-02
Applicant: QUALCOMM Incorporated
Inventor： Liang LI , Andrew Evan GRUBER , Jonnala Gadda NAGENDRA KUMAR , Thomas Edwin FRISINGER , Zilin YING , Srihari Babu ALLA
CPC classification number: G06F16/23 , G06F16/2282
Abstract: Aspects of the disclosure are directed to metadata updating. In accordance with one aspect, an apparatus includes an external memory unit configured for storing an original descriptor tag; a descriptor loading block coupled to the external memory, the descriptor loading block configured to fetch the original descriptor tag from the external memory for storage in an internal cache memory and further configured to compare the original descriptor tag stored in the internal cache memory to each of a plurality of original base values; and a remap table database coupled to the descriptor loading block, the remap table database configured to store the plurality of original base values, a plurality of updated base values and a plurality of updated miscellaneous base values.
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公开(公告)号：US20240078737A1
公开(公告)日：2024-03-07
申请号：US18320792
申请日：2023-05-19
Applicant: QUALCOMM Incorporated
Inventor： Jian LIANG , Andrew Evan GRUBER , Tao WANG , Xuefeng TANG , Vishwanath Shashikant NIKAM , Nigel POOLE , Kalyan Kumar BHIRAVABHATLA , Fei XU , Zilin YING
IPC: G06T15/00
CPC classification number: G06T15/005
Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.
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公开(公告)号：US20230019763A1
公开(公告)日：2023-01-19
申请号：US17758219
申请日：2020-01-31
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Chun YU , Chihong ZHANG , Thomas Edwin FRISINGER , Richard HAMMERSTONE , Zilin YING , Heng QI , Quanquan XU , Sheng GU
IPC: G06T1/60
Abstract: The present disclosure relates to methods and apparatus for graphics processing. For example, disclosed techniques facilitate improving bindless state processing at a graphics processor. Aspects of the present disclosure can receive, at a graphics processor, a shader program including a preamble section and a main instructions section. Aspects of the present disclosure can also execute, with a scalar processor dedicated to processing preamble sections, instructions of the preamble section to implement a bindless mechanism for loading constant data associated with the shader program. Additionally, aspects of the present disclosure can distribute the main instructions section and the constant data to a streaming processor for executing the shader program.
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公开(公告)号：US20220357983A1
公开(公告)日：2022-11-10
申请号：US17315205
申请日：2021-05-07
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Zilin YING , Gang ZHONG , Baoguang YANG , Yang YU , Yang XIA , Ravindra KUMAR , Chun YU , Eric DEMERS
IPC: G06F9/48 , G06F12/0875 , G06T1/20
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of workloads based on a workload order, each of the plurality of workloads being received in the workload order including at least a first workload and a second workload. The apparatus may also allocate one or more workloads of the plurality of workloads to one or more wave slots. Additionally, the apparatus may execute the one or more allocated workloads at the one or more wave slots, such that at least the first workload is executed at the first wave slot and the second workload is executed at the second wave slot. The apparatus may also allocate at least one other workload of the plurality of workloads to at least one previously-allocated wave slot of the one or more wave slots.
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Patent Agency Ranking
公开(公告)号：US20240289912A1
公开(公告)日：2024-08-29
申请号：US18175480
申请日：2023-02-27
Applicant: QUALCOMM Incorporated
Inventor： Nigel POOLE , Zilin YING , Xuhui MAO , Vijay Kumar DONTHIREDDY , Srihari Babu ALLA
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for an elimination cache. A graphics processor may obtain an indication of at least one state update from at least one CP associated with a graphics processor, where the at least one state update corresponds to one or more states in a set of states associated with the graphics processor. The graphics processor may determine whether the one or more states are stored in a cache associated with the graphics processor. The graphics processor may discard the at least one state update based on a determination that the one or more states are stored in the cache or update the cache based on a determination that the one or more states are not stored in the cache.
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公开(公告)号：US20210209717A1
公开(公告)日：2021-07-08
申请号：US16734252
申请日：2020-01-03
Applicant: QUALCOMM INCORPORATED
Inventor： Yun DU , Chun YU , Andrew Evan GRUBER , Zilin YING , Baoguang YANG
Abstract: Methods, systems, and devices for image processing are described. A device may determine, based on a test operation, to terminate a first wave associated with a first slot of a set of slots. The device may update a terminated wave bit associated with the first slot based on the determination to terminate the first wave. In some aspects, the device may update a number of invocations field associated with the first wave based on the determination to terminate the first wave. The device may release the first slot based on updating the terminated wave bit and the number of invocations field. In some examples, the device may output the number of invocations field to a rendering backend of the device based on the terminated wave bit.
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公开(公告)号：US20200312006A1
公开(公告)日：2020-10-01
申请号：US16364829
申请日：2019-03-26
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Chun YU , Chihong ZHANG , Hongjiang SHANG , Zilin YING , Fei WEI
Abstract: Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions.
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公开(公告)号：US20240046543A1
公开(公告)日：2024-02-08
申请号：US17817815
申请日：2022-08-05
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Eric DEMERS , Andrew Evan GRUBER , Chun YU , Baoguang YANG , Chihong ZHANG , Yuehai DU , Avinash SEETHARAMAIAH , Jonnala Gadda NAGENDRA KUMAR , Gang ZHONG , Zilin YING , Fei WEI
CPC classification number: G06T15/005 , G06T15/80
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.
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公开(公告)号：US20230267567A1
公开(公告)日：2023-08-24
申请号：US17652478
申请日：2022-02-24
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Zilin YING , Chunling HU , Baoguang YANG , Yang XIA , Gang ZHONG , Chun YU , Eric DEMERS
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for dynamic wave pairing. A graphics processor may allocate one or more GPU workloads to one or more wave slots of a plurality of wave slots. The graphics processor may select a first execution slot of a plurality of execution slots for executing the one or more GPU workloads. The selection may be based on one of a plurality of granularities. The graphics processor may execute, at the selected first execution slot, the one or more GPU workloads at the one of the plurality of granularities.
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