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    Zero block detection using adaptive rate model
    1.
    发明授权
    Zero block detection using adaptive rate model 有权

    公开(公告)号：US10587880B2

    公开(公告)日：2020-03-10

    申请号：US15940349

    申请日：2018-03-29

    Applicant: QUALCOMM Incorporated

    Inventor： Yang Yu ,  In Suk Chong ,  Xianglin Wang ,  Marta Karczewicz

    IPC: H04N19/147 ,  H04N19/14 ,  H04N19/194 ,  H04N19/64 ,  H04N19/176 ,  H04N19/124 ,  H04N19/172 ,  H04N19/149 ,  H04N19/132

    Abstract: A video coding device may be configured to estimate, based on a combination of a first parameter and a number of non-zero coefficients in a frame, a number of bits for non-zero coefficients of the frame, to encode the frame based on the estimated number of bits for the non-zero coefficients, to collect an actual number of bits used to encode the non-zero coefficients of the frame and an actual number of the non-zero coefficients in the frame, to update, based on the actual number of bits used to encode the non-zero coefficients of the frame and the actual number of non-zero coefficients in the frame, only the first parameter to form an updated first parameter, to form a rate estimation model using the updated first parameter and a second parameter, and to select, based on the rate estimation model, a coding mode for each block in the frame.

    Mode decision simplification for intra prediction
    3.
    发明授权
    Mode decision simplification for intra prediction 有权
    模式决策简化用于帧内预测

    公开(公告)号：US09426473B2

    公开(公告)日：2016-08-23

    申请号：US13756659

    申请日：2013-02-01

    Applicant: Qualcomm Incorporated

    Inventor： Yang Yu ,  Wei-Jung Chien ,  Xianglin Wang ,  Marta Karczewicz

    IPC: H04N19/00 ,  H04N19/11 ,  H04N19/50 ,  H04N19/176 ,  H04N19/147 ,  H04N19/19

    CPC classification number: H04N19/11 ,  H04N19/147 ,  H04N19/176 ,  H04N19/19 ,  H04N19/50

    Abstract: In general, techniques are described for reducing the complexity of mode selection when selecting from multiple, different prediction modes. A video coding device comprising a processor may perform the techniques. The processor may compute approximate costs for a pre-defined set of intra-prediction modes identified in a current set. The current set of intra-prediction modes may include fewer modes than a total number of intra-prediction modes. The processor may compare approximate costs computed for one or more most probable intra-prediction modes to a threshold and replace one or more of the intra-prediction modes of the current set with one or more most probable intra-prediction modes. The processor may perform rate distortion analysis with respect to each intra-prediction mode identified in the current set and perform intra-prediction coding with respect to the current block using a mode of the current set.

    Abstract translation: 一般来说，描述了当从多种不同的预测模式进行选择时降低模式选择的复杂度的技术。 包括处理器的视频编码装置可以执行这些技术。 处理器可以计算在当前集合中识别的预定义的帧内预测模式集合的近似成本。 当前的帧内预测模式集合可以包括比总内帧数据预测模式少的模式。 处理器可以将针对一个或多个最可能的帧内预测模式计算的近似成本与阈值进行比较，并用一个或多个最可能的帧内预测模式来替换当前集合的一个或多个帧内预测模式。 处理器可以针对当前集合中识别的每个帧内预测模式执行速率失真分析，并使用当前集合的模式对当前块执行帧内预测编码。

    ZERO BLOCK DETECTION USING ADAPTIVE RATE MODEL
    4.
    发明申请
    ZERO BLOCK DETECTION USING ADAPTIVE RATE MODEL 审中-公开

    公开(公告)号：US20180288420A1

    公开(公告)日：2018-10-04

    申请号：US15940393

    申请日：2018-03-29

    Applicant: QUALCOMM Incorporated

    Inventor： Yang Yu ,  In Suk Chong ,  Xianglin Wang ,  Marta Karczewicz

    IPC: H04N19/147 ,  H04N19/124 ,  H04N19/176 ,  H04N19/64

    Abstract: A video coding device may be configured to estimate, based on a combination of a first parameter and a number of non-zero coefficients in a frame, a number of bits for non-zero coefficients of the frame, to encode the frame based on the estimated number of bits for the non-zero coefficients, to collect an actual number of bits used to encode the non-zero coefficients of the frame and an actual number of the non-zero coefficients in the frame, to update, based on the actual number of bits used to encode the non-zero coefficients of the frame and the actual number of non-zero coefficients in the frame, only the first parameter to form an updated first parameter, to form a rate estimation model using the updated first parameter and a second parameter, and to select, based on the rate estimation model, a coding mode for each block in the frame.

    MODE DECISION SIMPLIFICATION FOR INTRA PREDICTION
    5.
    发明申请
    MODE DECISION SIMPLIFICATION FOR INTRA PREDICTION 有权
    用于内部预测的模式决策简化

    公开(公告)号：US20140219342A1

    公开(公告)日：2014-08-07

    申请号：US13756659

    申请日：2013-02-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： Yang Yu ,  Wei-Jung Chien ,  Xianglin Wang ,  Marta Karczewicz

    IPC: H04N7/26

    CPC classification number: H04N19/11 ,  H04N19/147 ,  H04N19/176 ,  H04N19/19 ,  H04N19/50

    Abstract: In general, techniques are described for reducing the complexity of mode selection when selecting from multiple, different prediction modes. A video coding device comprising a processor may perform the techniques. The processor may compute approximate costs for a pre-defined set of intra-prediction modes identified in a current set. The current set of intra-prediction modes may include fewer modes than a total number of intra-prediction modes. The processor may compare approximate costs computed for one or more most probable intra-prediction modes to a threshold and replace one or more of the intra-prediction modes of the current set with one or more most probable intra-prediction modes. The processor may perform rate distortion analysis with respect to each intra-prediction mode identified in the current set and perform intra-prediction coding with respect to the current block using a mode of the current set.

    Abstract translation: 一般来说，描述了当从多种不同的预测模式进行选择时降低模式选择的复杂度的技术。 包括处理器的视频编码装置可以执行这些技术。 处理器可以计算在当前集合中识别的预定义的帧内预测模式集合的近似成本。 当前的帧内预测模式集合可以包括比总内帧数据预测模式少的模式。 处理器可以将针对一个或多个最可能的帧内预测模式计算的近似成本与阈值进行比较，并用一个或多个最可能的帧内预测模式来替换当前集合的一个或多个帧内预测模式。 处理器可以针对当前集合中识别的每个帧内预测模式执行速率失真分析，并使用当前集合的模式对当前块执行帧内预测编码。

    Level decision in rate distortion optimized quantization
    7.
    发明授权
    Level decision in rate distortion optimized quantization 有权
    速率失真优化量化中的电平决定

    公开(公告)号：US09270986B2

    公开(公告)日：2016-02-23

    申请号：US13800155

    申请日：2013-03-13

    Applicant: QUALCOMM Incorporated

    Inventor： Yang Yu ,  Muhammed Zeyd Coban ,  Marta Karczewicz

    IPC: H04N7/26 ,  H04N19/126 ,  H04N19/147 ,  H04N19/172 ,  H04N19/149 ,  H04N19/18

    CPC classification number: H04N19/126 ,  H04N19/147 ,  H04N19/149 ,  H04N19/172 ,  H04N19/18

    Abstract: A computing device, such as a video encoder, determines an initial quantized level for a coefficient of a coefficient block and determines whether the coefficient is less than the product of the initial quantized level and a quantization step size value. In response to determining that the coefficient is less than the product of the initial quantized level and the quantization step size value, the computing device determines rate-distortion costs of quantizing the coefficient to be the initial quantized level for the coefficient, the initial quantized level minus one, and in some circumstances, 0. The computing device determines an actual quantized level for the coefficient based at least in part on the calculated rate-distortion costs and includes the actual quantized level in a quantized version of the coefficient block.

    Abstract translation: 诸如视频编码器的计算设备确定系数块系数的初始量化电平，并确定该系数是否小于初始量化电平与量化步长值的乘积。 响应于确定系数小于初始量化电平和量化步长值的乘积，计算装置确定将系数量化为系数的初始量化电平的速率失真成本，初始量化电平 在一些情况下，在一些情况下，计算装置至少部分地基于所计算的速率失真成本来确定系数的实际量化级别，并且包括系数块的量化版本中的实际量化级别。

    Systems and methods for low complexity forward transforms using mesh-based calculations
    9.
    发明授权
    Systems and methods for low complexity forward transforms using mesh-based calculations 有权
    使用基于网格的计算的低复杂度正向变换的系统和方法

    公开(公告)号：US09516345B2

    公开(公告)日：2016-12-06

    申请号：US14216369

    申请日：2014-03-17

    Applicant: QUALCOMM Incorporated

    Inventor： In Suk Chong ,  Yang Yu ,  Xianglin Wang ,  Marta Karczewicz

    IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/60 ,  H04N19/42 ,  H04N19/169 ,  H04N19/176

    CPC classification number: H04N19/60 ,  H04N19/42

    Abstract: Systems and methods for low complexity forward transforms using mesh-based calculations are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store video information. The video encoder further comprises a processor in communication with the memory. The processor is configured to decompose a transform into multiple transform stages. The processor is further configured to transform the video information using the multiple stages to determine a transform stage output at each transform stage. The processor is further configured to constrain the transform stage output at each transform stage to a predetermined bit depth. The processor is further configured to perform operations on the constrained transform output of a last stage of the multiple stages, wherein the operations are only available for use with data having the predetermined bit depth.

    Abstract translation: 本文描述了使用基于网格的计算的低复杂度正向变换的系统和方法。 在本公开中描述的主题的一个方面提供了一种视频编码器，其包括被配置为存储视频信息的存储器。 视频编码器还包括与存储器通信的处理器。 处理器被配置为将变换分解成多个变换阶段。 处理器还被配置为使用多级转换视频信息，以确定在每个变换阶段的变换级输出。 处理器还被配置为将每个变换级的变换级输出约束到预定位深度。 处理器还被配置为对多级的最后级的约束变换输出执行操作，其中操作仅可用于具有预定位深度的数据。

    Systems and methods for low complexity forward transforms using zeroed-out coefficients
    10.
    发明授权
    Systems and methods for low complexity forward transforms using zeroed-out coefficients 有权
    使用零值系数的低复杂度正向变换的系统和方法

    公开(公告)号：US09432696B2

    公开(公告)日：2016-08-30

    申请号：US14216086

    申请日：2014-03-17

    Applicant: QUALCOMM Incorporated

    Inventor： In Suk Chong ,  Yang Yu ,  Xianglin Wang ,  Marta Karczewicz

    IPC: H04N19/61 ,  H04N19/186 ,  H04N19/182 ,  H04N19/176 ,  H04N19/18 ,  H04N19/122 ,  H04N19/132

    CPC classification number: H04N19/61 ,  H04N19/122 ,  H04N19/132 ,  H04N19/14 ,  H04N19/176 ,  H04N19/18

    Abstract: Systems and methods for low complexity forward transforms using zeroed-out coefficients are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store a video block. The video encoder further comprises a processor in communication with the memory. The processor is configured to determine a full power value of the video block. The processor is further configured to determine a reduced transform coefficient matrix, wherein the reduced transform coefficient matrix comprises an inner region of zero or non-zero values of the same inner region of a full transform coefficient matrix and an outer region of zero values, wherein the reduced transform coefficient matrix and the full transform coefficient matrix have the same size. The processor is further configured to determine a partial power value of the video block using the reduced transform coefficient matrix. The processor is further configured to transform the video block from a pixel domain to a coefficient domain using the reduced transform coefficient matrix based on the full power value and partial power value. The processor is further configured to encode the transformed video block.

    Abstract translation: 本文描述了使用零缺失系数的低复杂度正向变换的系统和方法。 在本公开中描述的主题的一个方面提供了一种视频编码器，其包括被配置为存储视频块的存储器。 视频编码器还包括与存储器通信的处理器。 处理器被配置为确定视频块的全功率值。 处理器还被配置为确定缩小的变换系数矩阵，其中所述经简化的变换系数矩阵包括全变换系数矩阵和零值的外部区域的相同内部区域的零或非零值的内部区域，其中 减小的变换系数矩阵和全变换系数矩阵具有相同的大小。 处理器还被配置为使用缩减的变换系数矩阵来确定视频块的部分功率值。 处理器还被配置为使用基于全功率值和部分功率值的减小的变换系数矩阵将视频块从像素域变换到系数域。 处理器还被配置为对经变换的视频块进行编码。

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