公开(公告)号：US20180136967A1

公开(公告)日：2018-05-17

申请号：US15354791

申请日：2016-11-17

Applicant: QUALCOMM Incorporated

Inventor： Samar Asbe ,  Qazi Bashir ,  Vipul Gandhi ,  Chris Henroid ,  Mitchel Allen Humpherys ,  Olav Haugan ,  Daren Hall ,  Adam Openshaw ,  Priyesh Sanghvi ,  Brijen Raval

IPC: G06F9/46 ,  G06F21/53 ,  G06F9/455

CPC classification number: G06F9/45558 ,  G06F21/53 ,  G06F21/79 ,  G06F2009/45587

Abstract: In an aspect, an apparatus that includes a first security domain and at least a second security domain obtains, at a virtual machine of the first security domain, a stream identifier associated with the second security domain. The apparatus generates, at the virtual machine of the first security domain, a command to map the stream identifier associated with the second security domain to a first address translation context. The apparatus maps, at a hypervisor device, the first address translation context to a second address translation context that is associated with the second security domain of the stream identifier. The apparatus processes a stream of memory access transactions that includes the stream identifier based on at least the first address translation context or the second address translation context.

公开(公告)号：US20140181558A1

公开(公告)日：2014-06-26

申请号：US13726066

申请日：2012-12-22

Applicant: QUALCOMM INCORPORATED

Inventor： Ali Taha ,  Vipul Gandhi ,  Phani Babu Giddi

IPC: G06F1/32 ,  G06F12/02

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F1/3212 ,  G06F12/0238 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/174 ,  Y02D50/20

Abstract: A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory.

Abstract translation: 一种方法包括在包括易失性存储器和非易失性存储器的电子设备处启动从操作模式到休眠模式的转换。 响应于启动，将数据从易失性存储器复制到非易失性存储器，并且易失性存储器的一部分被禁用。 另一种方法包括确定在包括存储只读数据的第一副本的易失性存储器和存储只读数据的第二副本的非易失性存储器的电子设备处满足低性能模式条件。 只读数据的存储器映射从易失性存储器更新到非易失性存储器。 存储第一副本的易失性存储器的一部分被禁用，并且只读数据的访问被引导到非易失性存储器而不是易失性存储器。

公开(公告)号：US20240422336A1

公开(公告)日：2024-12-19

申请号：US18337116

申请日：2023-06-19

Applicant: QUALCOMM Incorporated

Inventor： Younghoon Kim ,  George Patsilaras ,  Shengqi Yang ,  Tomoyuki Naito ,  Giwon Kim ,  Vladan Andrijanic ,  Vipul Gandhi ,  Jaemoon Kim ,  Aravind Bhaskara ,  Mohit Hari Bhave ,  Rohit Thulasiram

IPC: H04N19/423 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172

Abstract: A method includes determining a picture type of a current picture, determining, based on the picture type of the current picture, whether to write the current picture in a dedicated chip memory or whether to write the current picture a non-dedicated system memory, and writing the current picture in the dedicated chip memory or the non-dedicated system memory based on the determining of whether to write the current picture in the dedicated chip memory or whether to write the current picture in the non-dedicated system memory.

公开(公告)号：US20230029696A1

公开(公告)日：2023-02-02

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US10514943B2

公开(公告)日：2019-12-24

申请号：US15354791

申请日：2016-11-17

Applicant: QUALCOMM Incorporated

Inventor： Samar Asbe ,  Qazi Bashir ,  Vipul Gandhi ,  Chris Henroid ,  Mitchel Allen Humpherys ,  Olav Haugan ,  Daren Hall ,  Adam Openshaw ,  Priyesh Sanghvi ,  Brijen Raval

IPC: G06F9/455 ,  G06F21/53 ,  G06F21/79

Abstract: In an aspect, an apparatus that includes a first security domain and at least a second security domain obtains, at a virtual machine of the first security domain, a stream identifier associated with the second security domain. The apparatus generates, at the virtual machine of the first security domain, a command to map the stream identifier associated with the second security domain to a first address translation context. The apparatus maps, at a hypervisor device, the first address translation context to a second address translation context that is associated with the second security domain of the stream identifier. The apparatus processes a stream of memory access transactions that includes the stream identifier based on at least the first address translation context or the second address translation context.

公开(公告)号：US09891694B2

公开(公告)日：2018-02-13

申请号：US13726066

申请日：2012-12-22

Applicant: QUALCOMM Incorporated

Inventor： Ali Taha ,  Vipul Gandhi ,  Phani Babu Giddi

IPC: G06F1/32 ,  G06F12/02

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F1/3212 ,  G06F12/0238 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/174 ,  Y02D50/20

Abstract: A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory.

公开(公告)号：US11907138B2

公开(公告)日：2024-02-20

申请号：US17646690

申请日：2021-12-31

Applicant: QUALCOMM Incorporated

Inventor： Hiral Nandu ,  Subbarao Palacharla ,  George Patsilaras ,  Alain Artieri ,  Simon Peter William Booth ,  Vipul Gandhi ,  Girish Bhat ,  Yen-Kuan Wu ,  Younghoon Kim

IPC: G06F12/123 ,  G06F9/30

CPC classification number: G06F12/123 ,  G06F9/30101

Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

公开(公告)号：US11803472B2

公开(公告)日：2023-10-31

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

CPC classification number: G06F12/084 ,  G06F1/3212 ,  G06F2212/62

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US20190026231A1

公开(公告)日：2019-01-24

申请号：US15658179

申请日：2017-07-24

Applicant: QUALCOMM Incorporated

Inventor： Sudeep Ravi KOTTILINGAL ,  Samar Asbe ,  Vipul Gandhi

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F9/455

Abstract: Various aspects include computing device methods for managed virtual machine memory access. Various aspects may include receiving a memory access request from a managed virtual machine having a virtual address, retrieving a first physical address for a stage 2 page table for a managing virtual machine, in which the stage 2 page table is stored in a physical memory space allocated to a hypervisor, retrieving a second physical address from an entry of the stage 2 page table for a stage 1 page table for a process executed by the managed virtual machine, in which the second physical address is for a physical memory space allocated to the managing virtual machine and the stage 1 page table is stored in that physical memory space, and retrieving a first intermediate physical address from an entry of the stage 1 page table for a translation of the virtual address.