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1.发明申请公开(公告)号：US20220224356A1
公开(公告)日：2022-07-14
申请号：US17649300
申请日：2022-01-28
Applicant: QUALCOMM Incorporated
Inventor： Shrinivas KUDEKAR , Thomas Joseph Richardson
Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
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公开(公告)号：US20200322085A1
公开(公告)日：2020-10-08
申请号：US16305255
申请日：2017-03-31
Applicant: QUALCOMM INCORPORATED
Inventor： Shrinivas KUDEKAR , Thomas Joseph RICHARDSON
Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits using a first code of length K to obtain bits for transmission via K channels, wherein the first code comprises a polar code, further encoding the bits in each of the K channels using a second code of length M, and transmitting the codeword.
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3.发明申请公开(公告)号：US20180367245A1
公开(公告)日：2018-12-20
申请号：US16011530
申请日：2018-06-18
Applicant: QUALCOMM Incorporated
Inventor： Joseph Binamira SORIAGA , Shrinivas KUDEKAR , Thomas RICHARDSON , Gabi SARKIS , Hari SANKAR , Jing JIANG
Abstract: The present disclosure provides self-decodable redundancy versions for a systematic code. An apparatus for wireless communications includes at least one processor coupled with a memory and comprising encoder circuitry configured to encode a set of information bits using a systematic code to generate an encoded bit stream with information bits and parity bits, and bit ordering circuitry configured to re-order bits in the encoded bit stream to distribute the information bits and the parity bits. The apparatus includes a transmitter configured to transmit the re-ordered bits in accordance with a radio technology via one or more antenna elements situated proximate the receiver.
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公开(公告)号：US20210058192A1
公开(公告)日：2021-02-25
申请号：US17090498
申请日：2020-11-05
Applicant: QUALCOMM Incorporated
Inventor： Thomas Joseph RICHARDSON , Shrinivas KUDEKAR
Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
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5.发明申请公开(公告)号：US20200052817A1
公开(公告)日：2020-02-13
申请号：US16655850
申请日：2019-10-17
Applicant: QUALCOMM Incorporated
Inventor： Shrinivas KUDEKAR , Thomas Joseph RICHARDSON
Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
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Patent Agency Ranking
公开(公告)号：US20190199475A1
公开(公告)日：2019-06-27
申请号：US16289113
申请日：2019-02-28
Applicant: QUALCOMM Incorporated
Inventor： Thomas Joseph RICHARDSON , Shrinivas KUDEKAR
CPC classification number: H04L1/0058 , H03M13/036 , H03M13/1148 , H03M13/116 , H03M13/616 , H03M13/6306 , H03M13/6505 , H03M13/6516 , H04L1/0041 , H04L1/0067 , H04L1/1812 , H04L1/1819
Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
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7.发明申请公开(公告)号：US20180358984A1
公开(公告)日：2018-12-13
申请号：US16003047
申请日：2018-06-07
Applicant: QUALCOMM Incorporated
Inventor： Thomas RICHARDSON , Joseph Binamira SORIAGA , Shrinivas KUDEKAR , Gabi SARKIS
CPC classification number: H03M13/1168 , H03M13/1137 , H03M13/114 , H03M13/1145 , H03M13/116 , H03M13/1185 , H03M13/618 , H03M13/6306 , H03M13/6393 , H03M13/6561 , H04L1/0057 , H04L5/0007
Abstract: Certain aspects of the present disclosure provide low-density parity-check (LDPC) codes having pairwise orthogonality of adjacent rows, and a new decoder that exploits the pairwise row orthogonality for flexible decoder scheduling without performance loss. An apparatus includes a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver. The apparatus includes at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a LDPC code to produce a set of information bits. The LDPC code is stored in the memory and defined by a base matrix having columns in which all adjacent rows are orthogonal in a last portion of the rows.
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公开(公告)号：US20190356337A1
公开(公告)日：2019-11-21
申请号：US16525307
申请日：2019-07-29
Applicant: QUALCOMM Incorporated
Inventor： Thomas Joseph RICHARDSON , Shrinivas KUDEKAR
Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.
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公开(公告)号：US20190280817A1
公开(公告)日：2019-09-12
申请号：US16422677
申请日：2019-05-24
Applicant: QUALCOMM Incorporated
Inventor： Shrinivas KUDEKAR , Thomas Joseph RICHARDSON
Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
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公开(公告)号：US20180205498A1
公开(公告)日：2018-07-19
申请号：US15919303
申请日：2018-03-13
Applicant: QUALCOMM Incorporated
Inventor： Shrinivas KUDEKAR , Thomas RICHARDSON
CPC classification number: H04L1/0063 , H03M13/09 , H03M13/098 , H03M13/13 , H03M13/3738 , H03M13/3977 , H03M13/612 , H04L1/0041 , H04L1/0045 , H04L1/0054 , H04L1/0057 , H04L1/0061
Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
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