公开(公告)号：US20170364140A1

公开(公告)日：2017-12-21

申请号：US15187426

申请日：2016-06-20

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Pawan Chhabra ,  Navid Toosizadeh ,  Sreekanth Nallagatla ,  Shih-Hsin Jason Hu

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/3296 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324

Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.

公开(公告)号：US10656203B1

公开(公告)日：2020-05-19

申请号：US16278420

申请日：2019-02-18

Applicant: QUALCOMM Incorporated

Inventor： Punit Kishore ,  Jais Abraham ,  Pawan Chhabra

IPC: G01R31/317 ,  G06F13/42 ,  G01R31/3177 ,  H03K19/20

Abstract: Certain aspects of the present disclosure provide an apparatus for processor core testing. The apparatus generally includes a high-speed input-output (HSIO) interface, a general purpose input-output (GPIO) interface, a multiplexer having a first input coupled to the GPIO interface, a test controller coupled between the HSIO interface and a second input of the multiplexer, and one or more processor cores coupled to the output of the multiplexer.

公开(公告)号：US11494248B2

公开(公告)日：2022-11-08

申请号：US16722861

申请日：2019-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： Rakesh Misra ,  Rohit Gupta ,  Shubham Maheshwari ,  Pawan Chhabra

IPC: G06F11/07 ,  G06F9/4401 ,  G06F15/78 ,  G06F1/24 ,  G06F11/14 ,  G06F11/30 ,  G06F1/3203

Abstract: A warm mission-mode reset may be performed in a portable computing device. Assertion of a signal indicating an error condition may be detected. In response to detection of the signal indicating an error condition, a signal indicating a request to preserve memory contents may be provided to a DRAM subsystem. Then, in response to a signal acknowledging the DRAM subsystem is preserving the memory contents, a system reset signal may be asserted.

公开(公告)号：US10359833B2

公开(公告)日：2019-07-23

申请号：US15187426

申请日：2016-06-20

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Pawan Chhabra ,  Navid Toosizadeh ,  Sreekanth Nallagatla ,  Shih-Hsin Jason Hu

IPC: G06F1/3206 ,  G06F1/3296 ,  G06F1/08 ,  G06F1/3228 ,  G06F1/324

Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.