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    USB DEVICE WITH CLOCK DOMAIN CORRELATION
    1.
    发明申请
    USB DEVICE WITH CLOCK DOMAIN CORRELATION 审中-公开

    公开(公告)号：US20190025872A1

    公开(公告)日：2019-01-24

    申请号：US15652516

    申请日：2017-07-18

    Applicant: QUALCOMM Incorporated

    Inventor： Ren Li ,  Peter Shah ,  Matthew Sienko ,  Hui-ya Liao Nelson ,  Stefan Rohrer ,  Arash Mehrabi ,  Stefan Mueller ,  Ralf Herz ,  Magesh Hariharan ,  Maoxin Wei

    IPC: G06F1/12 ,  G06F13/42

    Abstract: Methods and USB devices correlating clock domains are presented. A USB device includes at least one signal line adapted to carry signals in a first clock domain. The signals are received from a USB host. A clock operates a second clock domain. A periodic packet detection circuit detects a missing periodic packet from the signals received in the first clock domain. A device controller correlates a USB operation in the second clock domain with the first clock domain based on the periodic packet detection circuit detecting the missing periodic packet. A USB device includes at least one signal line carrying UTMI or ULPI signaling. A USB controller decodes packet identification from the UTMI or ULPI signaling. A periodic packet detection circuit, separate from the USB controller, decodes packet identification from the UTMI or ULPI signaling.

    SYSTEM AND METHOD OF SPEECH RECOGNITION
    5.
    发明申请
    SYSTEM AND METHOD OF SPEECH RECOGNITION 有权
    语音识别系统与方法

    公开(公告)号：US20160180837A1

    公开(公告)日：2016-06-23

    申请号：US14573402

    申请日：2014-12-17

    Applicant: QUALCOMM Incorporated

    Inventor： Bengt Stefan Gustavsson ,  Magesh Hariharan ,  Siva Pavan Kumar Mitnala ,  John Michael Murray ,  Peter Jivan Shah

    IPC: G10L15/08

    CPC classification number: G10L15/285 ,  G06F1/3203 ,  G06F3/16 ,  G10L15/08 ,  G10L15/22 ,  G10L15/28 ,  G10L2015/088 ,  G11B20/10527 ,  G11B2020/1062

    Abstract: A particular apparatus includes a coder/decoder (CODEC) including a first processor and a first buffer. The first processor is configured to analyze audio data samples to detect a keyword. The CODEC is configured to store a set of audio data samples at the first buffer. The apparatus also includes an application processor configured to receive the set of audio data samples from the CODEC via a bus and configured to initialize a speech recognition engine (SRE) based on the set of audio data samples. The application processor is configured to initialize the bus based on an indication from the CODEC that the keyword is detected.

    Abstract translation: 特定装置包括包括第一处理器和第一缓冲器的编码器/解码器（CODEC）。 第一处理器被配置为分析音频数据样本以检测关键字。 CODEC被配置为在第一缓冲器处存储一组音频数据样本。 该设备还包括应用处理器，其被配置为经由总线从CODEC接收该组音频数据样本，并且被配置为基于该组音频数据样本来初始化语音识别引擎（SRE）。 应用处理器被配置为基于来自CODEC的指示来初始化总线以检测关键字。

    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES
    6.
    发明申请
    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES 审中-公开

    公开(公告)号：US20160142455A1

    公开(公告)日：2016-05-19

    申请号：US14541577

    申请日：2014-11-14

    Applicant: QUALCOMM Incorporated

    Inventor： Magesh Hariharan ,  Lior Amarilio ,  Julio Arceo ,  Aris Balatsos ,  Hans Georg Gruber

    IPC: H04L29/06 ,  H04R3/12

    CPC classification number: H04L65/4069 ,  G06F3/162 ,  G06F13/4291 ,  H04R3/12 ,  H04R5/04 ,  H04R2420/09 ,  H04R2499/11

    Abstract: Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES
    9.
    发明申请
    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES 审中-公开
    多声道音频对准方案

    公开(公告)号：US20160142454A1

    公开(公告)日：2016-05-19

    申请号：US14541557

    申请日：2014-11-14

    Applicant: QUALCOMM Incorporated

    Inventor： Magesh Hariharan ,  Lior Amarilio ,  Julio Arceo ,  Aris Balatsos ,  Hans Georg Gruber

    IPC: H04L29/06 ,  H04R3/12

    CPC classification number: H04L65/4069 ,  G06F3/162 ,  G06F3/165 ,  G06F13/4291 ,  H04L65/604 ,  H04R3/12 ,  H04R5/04 ,  H04R2420/09 ,  H04R2499/11

    Abstract: Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

    Abstract translation: 公开了多声道音频对准方案。 本公开的一个方面提供了音频源在多个相关音频通道上的累积。 相关的音频通道表示它们的相互关联性，当所有相关的音频通道都具有要发送的数据时，源将数据释放到串行低功率芯片间媒体总线（SLIMbus）的时隙上，使得相关的音频通道 在时隙的给定分段窗口内。 在每个分段窗口的边界处重复该累积。 类似地，可以在音频接收器处执行累加。 音频接收器内的组件只能从所有相关接收器的状态信号指示已达到预定义的阈值时才读取接收到的数据。 通过提供这种累积选项，可以在多个音频数据通道之间保持音频保真度。

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