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公开(公告)号：US09852536B2
公开(公告)日：2017-12-26
申请号：US14452281
申请日：2014-08-05
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Guofang Jiao , Yunshan Kong , Javier Ignacio Girado
CPC classification number: G06T15/005 , G06T1/20 , G06T1/60 , G06T5/20 , G06T11/40 , G06T15/04 , G06T2200/28
Abstract: This disclosure describes techniques for performing high order filtering in a graphics processing unit (GPU). In examples of the disclosure, high order filtering may be implemented on a modified texture engine of a GPU using a single shader instruction. The modified texture engine may be configured to fetch all source pixels needed for the high order filtering and blend them together with pre-loaded filtering weights.
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公开(公告)号：US20160019027A1
公开(公告)日：2016-01-21
申请号：US14331991
申请日：2014-07-15
Applicant: QUALCOMM Incorporated
Inventor： Lin Chen , Andrew Evan Gruber , Guofang Jiao , Chiente Ho , Pramod Vasant Argade
IPC: G06F5/01
CPC classification number: G06F7/49936 , G06F7/552 , G06F2207/5525 , G09C1/00 , H04L2209/12
Abstract: At least one processor may receive components of a vector, wherein each of the components of the vector comprises at least an exponent. The at least one processor may further determine a maximum exponent out of respective exponents of the components of the vector, and may determine a scaling value based at least in part on the maximum exponent. An arithmetic logic unit of the at least one processor may scale the vector, by subtracting the scaling value from each of the respective exponents of the components of the vector.
Abstract translation: 至少一个处理器可以接收向量的分量，其中矢量的每个分量包括至少一个指数。 所述至少一个处理器可以进一步确定向量的分量的相应指数中的最大指数，并且可以至少部分地基于最大指数来确定缩放值。 所述至少一个处理器的算术逻辑单元可以通过从所述矢量的各个成分的各指数中减去所述缩放值来缩放所述向量。
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公开(公告)号：US20180165092A1
公开(公告)日：2018-06-14
申请号：US15379195
申请日：2016-12-14
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Liang Han , Lin Chen , Chihong Zhang , Hongjiang Shang , Jing Wu , Zilin Ying , Chun Yu , Guofang Jiao , Andrew Gruber , Eric Demers
Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.
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公开(公告)号：US09123168B2
公开(公告)日：2015-09-01
申请号：US13754005
申请日：2013-01-30
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Nariman Moezzi Madani , Vineet Goel , Usame Ceylan , Guofang Jiao
CPC classification number: G06T17/20 , G06T15/005
Abstract: Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.
Abstract translation: 描述了细分的系统和方法。 为了细分，镶嵌单元可以将域划分成多个部分，其中至少一个部分是连续部分。 细分单元可以输出连续部分内沿着对角条纹的基元的域坐标，以增加对应于域坐标的修补坐标被存储在重用缓冲器中的可能性。
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公开(公告)号：US09799089B1
公开(公告)日：2017-10-24
申请号：US15162272
申请日：2016-05-23
Applicant: QUALCOMM Incorporated
Inventor： Lin Chen , Yun Du , Andrew Evan Gruber , Guofang Jiao , Chun Yu , David Rigel Garcia Garcia
Abstract: A method for processing data in a graphics processing unit including receiving a code block of instructions common to a plurality of groups of threads of a shader, executing the code block of instructions common to the plurality of groups of threads of the shader creating a result by a first group of threads of the plurality of groups of threads, storing the result of the code block of instructions common to the plurality of groups of threads of the shader in on-chip random access memory (RAM), the on-chip RAM accessible by each of the plurality of groups of threads, and upon a determination that storing the result of the code block of instructions common to the plurality of groups of threads of the shader has completed, returning the result of the code block of instructions common to the plurality of groups of threads of the shader from on-chip RAM.
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Patent Agency Ranking
公开(公告)号：US09454841B2
公开(公告)日：2016-09-27
申请号：US14452326
申请日：2014-08-05
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Guofang Jiao , Yunshan Kong , Javier Ignacio Girado
CPC classification number: G06T15/005 , G06T1/20 , G06T5/20 , G06T11/40 , G06T2200/28
Abstract: This disclosure describes techniques for performing high order filtering in a graphics processing unit (GPU). In examples of the disclosure, high order filtering may be implemented on a modified texture engine of a GPU using a single shader instruction. The modified texture engine may be configured to fetch all source pixels needed for the high order filtering and blend them together with pre-loaded filtering weights.
Abstract translation: 本公开描述了用于在图形处理单元（GPU）中执行高阶滤波的技术。 在本公开的示例中，可以使用单个着色器指令在GPU的修改的纹理引擎上实现高阶滤波。 修改的纹理引擎可以被配置为获取高阶过滤所需的所有源像素，并将它们与预加载的滤波权重相混合。
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公开(公告)号：US20160042549A1
公开(公告)日：2016-02-11
申请号：US14452281
申请日：2014-08-05
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Guofang Jiao , Yunshan Kong , Javier Ignacio Girado
CPC classification number: G06T15/005 , G06T1/20 , G06T1/60 , G06T5/20 , G06T11/40 , G06T15/04 , G06T2200/28
Abstract: This disclosure describes techniques for performing high order filtering in a graphics processing unit (GPU). In examples of the disclosure, high order filtering may be implemented on a modified texture engine of a GPU using a single shader instruction. The modified texture engine may be configured to fetch all source pixels needed for the high order filtering and blend them together with pre-loaded filtering weights.
Abstract translation: 本公开描述了用于在图形处理单元（GPU）中执行高阶滤波的技术。 在本公开的示例中，可以使用单个着色器指令在GPU的修改的纹理引擎上实现高阶滤波。 修改的纹理引擎可以被配置为获取高阶过滤所需的所有源像素，并将它们与预加载的滤波权重相混合。
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公开(公告)号：US20150022534A1
公开(公告)日：2015-01-22
申请号：US14506959
申请日：2014-10-06
Applicant: QUALCOMM Incorporated
Inventor： YUN DU , Guofang Jiao , Chun Yu , Alexei Vladimirovich Bourd
IPC: G06T1/20
CPC classification number: G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
Abstract: A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
Abstract translation: 描述能够有效执行算术运算和计算基本功能的图形处理器。 图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。 图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。 四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。 单个基本功能单元可以一次操作一个像素的一个分量。 使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。
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公开(公告)号：US10558460B2
公开(公告)日：2020-02-11
申请号：US15379195
申请日：2016-12-14
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Liang Han , Lin Chen , Chihong Zhang , Hongjiang Shang , Jing Wu , Zilin Ying , Chun Yu , Guofang Jiao , Andrew Gruber , Eric Demers
Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.
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公开(公告)号：US09697580B2
公开(公告)日：2017-07-04
申请号：US14537589
申请日：2014-11-10
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Andrew Evan Gruber , Guofang Jiao , Zhenyu Qi , Gregory Steve Pitarys , Scott William Nolan
CPC classification number: G06T1/20 , G09G5/18 , G09G2330/022
Abstract: This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.
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