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    Boost and LDO hybrid converter with dual-loop control
    2.
    发明授权
    Boost and LDO hybrid converter with dual-loop control 有权

    公开(公告)号：US10411599B1

    公开(公告)日：2019-09-10

    申请号：US15937947

    申请日：2018-03-28

    Applicant: QUALCOMM Incorporated

    Inventor： Chunlei Shi ,  Jongrit Lerdworatawee ,  Yu Pu

    IPC: H02M3/156 ,  H02M3/158 ,  G05F1/26 ,  H02M1/00 ,  G05F1/45

    Abstract: A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

    Power Receiving Unit For Charging While In Pre-Overvoltage Protection
    3.
    发明申请
    Power Receiving Unit For Charging While In Pre-Overvoltage Protection 审中-公开

    公开(公告)号：US20180254631A1

    公开(公告)日：2018-09-06

    申请号：US15451173

    申请日：2017-03-06

    Applicant: QUALCOMM Incorporated

    Inventor： Mark White, II ,  William Henry Von Novak, III ,  Chunlei Shi

    IPC: H02H9/04 ,  H02J50/12 ,  H02J7/02

    CPC classification number: H02H9/042 ,  A61N1/3787 ,  H02H3/04 ,  H02H9/041 ,  H02J7/025 ,  H02J50/12 ,  H02J2007/0037

    Abstract: The present disclosure describes a power receiving unit for charging while in pre-overvoltage protection. In some aspects, reduced operation of an electronic implant device is initiated before resorting to overvoltage protection. In aspects, the electronic implant device has a power receiving unit capable of receiving power wirelessly from a wireless power transmitter. The power receiving unit can also detect an induced voltage and trigger pre-overvoltage protection when the detected voltage reaches a pre-overvoltage protection threshold. Additionally, a power management integrated circuit (PMIC) of the electronic implant device draws power from the power receiving unit to carry out corresponding functionality. The PMIC also obtains an indication when the detected voltage reaches the pre-overvoltage protection threshold. Based on the indication, the PMIC may reduce the power it draws from the power receiving unit to a predefined, reduced level instead of a normal operating level.

    Charge-recycling circuits
    4.
    发明授权
    Charge-recycling circuits 有权
    充电回收电路

    公开(公告)号：US09525337B2

    公开(公告)日：2016-12-20

    申请号：US14260592

    申请日：2014-04-24

    Applicant: QUALCOMM Incorporated

    Inventor： Seyed Mahmoudreza Saadat ,  Chunlei Shi ,  Chenchang Zhan

    IPC: H03K3/00 ,  H02M3/07 ,  G05F1/577 ,  G05F1/575

    CPC classification number: H02M3/07 ,  G05F1/575 ,  G05F1/577

    Abstract: In one embodiment, a circuit comprises a first load circuit coupled to a first input voltage. A current sinking circuit is coupled to an output of the first load circuit. A second load circuit is coupled to ground. A current sourcing circuit is coupled between a second input voltage and an output of the second load circuit. A charge-recycling circuit is coupled between the output of the first load circuit and the output of the second load circuit to provide current from the current sinking circuit to the output of the current sourcing circuit to reduce current through the current sourcing circuit. The charge-recycling circuit can be a charge pump.

    Abstract translation: 在一个实施例中，电路包括耦合到第一输入电压的第一负载电路。 电流吸收电路耦合到第一负载电路的输出。 第二负载电路耦合到地。 电流源电路耦合在第二输入电压和第二负载电路的输出之间。 电荷回收电路耦合在第一负载电路的输出和第二负载电路的输出之间，以提供从电流吸收电路到电流源电路的输出的电流，以减少通过电流源电路的电流。 充电回收电路可以是电荷泵。

    CHARGE-RECYCLING CIRCUITS
    5.
    发明申请
    CHARGE-RECYCLING CIRCUITS 有权
    充电回路电路

    公开(公告)号：US20150311783A1

    公开(公告)日：2015-10-29

    申请号：US14260592

    申请日：2014-04-24

    Applicant: QUALCOMM Incorporated

    Inventor： Seyed Mahmoudreza Saadat ,  Chunlei Shi ,  Chenchang Zhan

    IPC: H02M3/07 ,  G05F1/577

    CPC classification number: H02M3/07 ,  G05F1/575 ,  G05F1/577

    Abstract: In one embodiment, a circuit comprises a first load circuit coupled to a first input voltage. A current sinking circuit is coupled to an output of the first load circuit. A second load circuit is coupled to ground. A current sourcing circuit is coupled between a second input voltage and an output of the second load circuit. A charge-recycling circuit is coupled between the output of the first load circuit and the output of the second load circuit to provide current from the current sinking circuit to the output of the current sourcing circuit to reduce current through the current sourcing circuit. The charge-recycling circuit can be a charge pump.

    Abstract translation: 在一个实施例中，电路包括耦合到第一输入电压的第一负载电路。 电流吸收电路耦合到第一负载电路的输出。 第二负载电路耦合到地。 电流源电路耦合在第二输入电压和第二负载电路的输出之间。 电荷回收电路耦合在第一负载电路的输出和第二负载电路的输出之间，以提供从电流吸收电路到电流源电路的输出的电流，以减少通过电流源电路的电流。 充电回收电路可以是电荷泵。

    METHOD AND APPARATUS FOR ADVANCED PULSE SKIPPING CONTROL IN BUCK REGULATORS
    6.
    发明申请
    METHOD AND APPARATUS FOR ADVANCED PULSE SKIPPING CONTROL IN BUCK REGULATORS 审中-公开
    BUCK调节器中高级脉冲跳闸控制的方法和装置

    公开(公告)号：US20140253080A1

    公开(公告)日：2014-09-11

    申请号：US13793703

    申请日：2013-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xufeng Jiang ,  Chunlei Shi ,  Sugato Mukherjee

    IPC: G05F1/62

    CPC classification number: G05F1/62 ,  H02M3/156 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0025 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

    Abstract: A method and apparatus for determining the entry and exit from a pulse skipping mode in a power supply is provided. The power supply may incorporate a buck regulator. The method begins when current is sensed at an inductor of a power supply. This sensed current is then compared with a predetermined threshold current value. If the comparison reveals that the current is below the predetermined threshold current value, a pulse skipping mode is entered. If the current is found to be above the predetermined threshold the pulse skipping mode is not entered and normal operation continues. The apparatus includes a transconductance amplifier, an offset voltage source, a reference power supply reference voltage source, first and second voltage comparators, and a processor.

    Abstract translation: 提供了一种用于确定电源中的脉冲跳过模式的进入和退出的方法和装置。 电源可以并入降压调节器。 当在电源的电感器处感测到电流时，该方法开始。 然后将该感测电流与预定的阈值电流值进行比较。 如果比较显示电流低于预定阈值电流值，则输入脉冲跳跃模式。 如果发现电流高于预定阈值，则不进入脉冲跳跃模式，并且正常操作继续。 该装置包括跨导放大器，偏移电压源，参考电源参考电压源，第一和第二电压比较器以及处理器。

    Charge-recycling circuits including switching power stages with floating rails
    9.
    发明授权
    Charge-recycling circuits including switching power stages with floating rails 有权
    充电回收电路包括带有浮动导轨的开关功率级

    公开(公告)号：US09276562B2

    公开(公告)日：2016-03-01

    申请号：US14260733

    申请日：2014-04-24

    Applicant: QUALCOMM Incorporated

    Inventor： Seyed Mahmoudreza Saadat ,  Chunlei Shi ,  Chenchang Zhan

    IPC: H03K3/00 ,  H03K3/012 ,  H03K17/56 ,  H03K17/687

    CPC classification number: H03K3/012 ,  H03K17/56 ,  H03K17/6874 ,  H03K2217/0036 ,  H03K2217/0081

    Abstract: In one embodiment, a circuit comprises a first switching transistor and a second switching transistor. The first switching transistor and the second switching transistor are coupled in series between an input voltage and ground and having a common node therebetween to provide a switching output. A first switching circuit selective couples a gate of the first switching transistor to the input voltage and a first mid-level voltage supply. A second switching circuit selectively couples a gate of the second switching transistor to a second mid-level voltage supply and ground. A charge-recycling circuit is coupled to the gate of the first switching transistor, the gate of the second switching transistor, the first mid-level voltage supply, and the second mid-level voltage supply to selectively recycle charge between the first mid-level voltage supply and the second mid-level voltage supply.

    Abstract translation: 在一个实施例中，电路包括第一开关晶体管和第二开关晶体管。 第一开关晶体管和第二开关晶体管串联耦合在输入电压和地之间并且在它们之间具有公共节点以提供开关输出。 第一开关电路将第一开关晶体管的栅极选择性地耦合到输入电压和第一中间电平电压。 第二开关电路将第二开关晶体管的栅极选择性地耦合到第二中间电平电压源并接地。 电荷再循环电路耦合到第一开关晶体管的栅极，第二开关晶体管的栅极，第一中间电平电压和第二中间电平电压，以选择性地在第一中间电平 电压供应和第二中间电压供应。

    Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power
    10.
    发明授权
    Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power 有权

    公开(公告)号：US10581441B2

    公开(公告)日：2020-03-03

    申请号：US15706449

    申请日：2017-09-15

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Pu ,  Jongrit Lerdworatawee ,  Chunlei Shi

    IPC: H03L7/06 ,  H03L7/187 ,  H03L7/07 ,  H03L7/197 ,  G01R31/317 ,  H03L7/099 ,  H02M3/335 ,  H03K3/0231

    Abstract: A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

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