公开(公告)号：US20160170877A1

公开(公告)日：2016-06-16

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： GEORGE PATSILARAS ,  BOHUSLAV RYCHLIK ,  ANDREW EDMUND TURNER ,  KRIS TIRI ,  JEONG-HO WOO ,  ANWAR ROHILLAH ,  FENG WANG ,  MOINUL KHAN ,  SUBBARAO PALACHARLA

IPC: G06F12/08 ,  G06F13/16 ,  G06F9/46 ,  G06F1/32

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US20170024316A1

公开(公告)日：2017-01-26

申请号：US14807840

申请日：2015-07-23

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  BOHUSLAV RYCHLIK

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F9/46 ,  G06F9/5088 ,  G06F12/0815 ,  G06F2212/314 ,  G06F2212/621

Abstract: Systems, methods, and computer programs are disclosed for scheduling tasks in a heterogeneous processor cluster architecture in a portable computing device. One embodiment is a system comprising a first processor cluster and a second processor cluster. The first processor cluster comprises a first shared cache, and the second processor cluster comprises a second shared cache. The system further comprises a controller in communication with the first and second processor clusters for performing task migration between the first and second processor clusters. The controller initiates execution of a task on a first processor in the first processor cluster. The controller monitors a processor workload for the first processor and a cache demand associated with the first shared cache while the task is running on the first processor in the first processor cluster. The controller migrates the task to the second processor cluster based on the processor workload and the cache demand.

Abstract translation: 公开了用于在便携式计算设备中的异构处理器集群架构中调度任务的系统，方法和计算机程序。 一个实施例是包括第一处理器集群和第二处理器集群的系统。 第一处理器集群包括第一共享高速缓存，并且第二处理器集群包括第二共享高速缓存。 该系统还包括与第一和第二处理器集群通信的控制器，用于执行第一和第二处理器集群之间的任务迁移。 控制器在第一处理器集群中的第一处理器上启动任务的执行。 当任务在第一处理器集群中的第一处理器上运行时，控制器监视第一处理器的处理器工作负载和与第一共享高速缓存相关联的高速缓存需求。 控制器根据处理器工作负载和缓存需求将任务迁移到第二个处理器集群。

公开(公告)号：US20160210239A1

公开(公告)日：2016-07-21

申请号：US14598049

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： FENG WANG ,  BOHUSLAV RYCHLIK ,  MOINUL KHAN

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0835 ,  G06F12/0868 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/62 ,  Y02D10/13

Abstract: Systems and methods for improved operation of a victim cache in a portable computing device (PCD) are presented. A lower level cache is operated as a victim to an upper level cache, the lower level cache containing a plurality of cache lines. A filter is operated in association with the lower level victim cache, and reflects the cache lines contained in the victim cache. For a miss at the upper level cache, the filter is checked to determine if the requested cache line is in the victim cache. If checking the filter determines that the requested cache line is in the victim cache the requested cache line is retrieved from the victim cache. If checking the filter determines that the request cache line is not in the victim cache, the victim cache is bypassed and the cache line is requested from a memory controller.

Abstract translation: 提出了用于改进便携式计算设备（PCD）中的受害者缓存的操作的系统和方法。 低级缓存作为高级缓存的受害者操作，下级缓存包含多条高速缓存行。 过滤器与较低级别的受害者缓存相关联地操作，并且反映包含在受害者缓存中的高速缓存行。 对于高级缓存中的缺失，将检查过滤器以确定所请求的高速缓存行是否位于受害缓存中。 如果检查过滤器确定请求的高速缓存行在受害缓存中，则从受害缓存中检索所请求的高速缓存行。 如果检查过滤器确定请求高速缓存行不在受害者缓存中，则会绕过受害者缓存，并从存储控制器请求缓存行。

公开(公告)号：US20160210230A1

公开(公告)日：2016-07-21

申请号：US14597992

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： FENG WANG ,  BOHUSLAV RYCHLIK ,  MOINUL KHAN

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0848 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/282 ,  G06F2212/283 ,  G06F2212/6012 ,  G06F2212/604

Abstract: Systems and methods for adaptive implementation of victim cache modes in a portable computing device (PCD) are presented. In operation, an upper level cache is partitioned into a main portion and a sample portion; and a lower level cache is partitioned into a corresponding main portion and sample portion in communication with the main portion and sample portion of the upper level cache. A victim mode sample data set and a normal mode sample data set are obtained from the lower level cache. Based on the victim mode and a normal mode sample data sets, a determination is made whether to operate the lower level cache as a victim to the upper level cache. The main portion of lower level cache is caused to operate either as a victim or non-victim to the main portion of the upper level cache in accordance with the determination.

Abstract translation: 提出了在便携式计算设备（PCD）中自适应实现受害者缓存模式的系统和方法。 在操作中，上级缓存被分割成主要部分和样本部分; 并且下级缓存被分割成与上级高速缓存的主要部分和采样部分通信的对应主要部分和采样部分。 从下级缓存获得受害者模式样本数据集和正常模式样本数据集。 基于受害者模式和正常模式的采样数据集，确定是否将较低级别的高速缓存操作为上级缓存的受害者。 下级缓存的主要部分根据该确定被作为高级缓存的主要部分作为受害者或不受害者操作。

公开(公告)号：US20170108914A1

公开(公告)日：2017-04-20

申请号：US14885803

申请日：2015-10-16

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  BOHUSLAV RYCHLIK

IPC: G06F1/32 ,  G06F12/06 ,  H04W52/02

CPC classification number: G06F1/3287 ,  G06F12/0607 ,  G06F12/0623 ,  G06F2212/1016 ,  G06F2212/1028 ,  H04W52/0261 ,  Y02D10/13 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/168

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method comprises configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance tasks, and the linear region comprises a linear address space for relatively lower power tasks. A boundary is defined between the linear region and the interleaved region using a sliding threshold address. A request is received from a process for a virtual memory page. The request comprises a preference for power savings or performance. The virtual memory page is assigned to a free physical page in the linear region or the interleaved region based on the preference for power savings or performance using the sliding threshold address.

公开(公告)号：US20150100746A1

公开(公告)日：2015-04-09

申请号：US14045784

申请日：2013-10-03

Applicant: Qualcomm Incorporated

Inventor： BOHUSLAV RYCHLIK ,  FENG WANG ,  ANWAR ROHILLAH ,  SIMON BOOTH

IPC: G06F12/06

CPC classification number: G06F12/0607

Abstract: Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

Abstract translation: 公开了跨物理通道具有不均匀存储容量的存储器空间的物理信道的均匀交织的系统和方法。 交织器布置成与一个或多个处理器和系统存储器通信。 交织器识别由存储器通道支持的存储器空间中的位置，并响应于定义具有期望存储容量的虚拟扇区的逻辑。 响应于访问存储器空间的请求，交织器跨虚拟扇区均匀地访问非对称存储容量。