公开(公告)号：US20130254579A1

公开(公告)日：2013-09-26

申请号：US13844204

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Amy DERBYSHIRE ,  Francis NGAI ,  Ali TAHA ,  Eric MIKUTEIT ,  Michael Lee MCCLOUD ,  Amit MAHAJAN ,  David CORONEL ,  Prashanth AKULA ,  Todd SUTTON ,  Hardik PATEL ,  Hector CORLETO

IPC: G06F1/28

CPC classification number: G06F1/28 ,  G06F1/26 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/329 ,  G06F11/3013 ,  G06F11/3062 ,  H04W52/0277 ,  Y02D10/174 ,  Y02D10/24 ,  Y02D70/1222 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/23

Abstract: A method and system for managing electrical current within a portable computing device (“PCD”) includes assigning a priority to two or more communications supported by the PCD. A present level of a power supply for the PCD may be monitored by a communications power (“CP”) manager module. Next, the CP manager module may determine if the two or more communications may be transmitted at the present level of the power supply. If the two or more communications cannot be transmitted at the present level of the power supply, then the CP manager module may determine if a timing of at least one of the communications may be adjusted. The CP manager module may also determine a theoretical power level adjustment for at least one of the communications. The two or more communications may be transmitted with any calculated timing off sets and power level adjustments.

Abstract translation: 用于管理便携式计算设备（“PCD”）内的电流的方法和系统包括将优先级分配给由PCD支持的两个或多个通信。 PCD的电源的当前电平可以由通信电源（“CP”）管理器模块监视。 接下来，CP管理器模块可以确定两个或多个通信是否可以在电源的当前级别发送。 如果两个或更多个通信不能在电源的当前级别发送，则CP管理器模块可以确定是否可以调整至少一个通信的定时。 CP管理器模块还可以确定至少一个通信的理论功率电平调整。 两个或更多个通信可以用任何计算的定时关闭集和功率电平调整来发送。

公开(公告)号：US20160246362A1

公开(公告)日：2016-08-25

申请号：US15052786

申请日：2016-02-24

Applicant: QUALCOMM Incorporated

Inventor： Suresh SUGUMAR ,  Jeffrey GEMAR ,  Ali TAHA ,  Amy DERBYSHIRE ,  Tao XUE ,  Mohammad TAMJIDI ,  Rajat MITTAL

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3885 ,  Y02D10/152

Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Abstract translation: 一种装置包括第一电路和共享指令流的第二电路。 电压控制器电路被配置为响应于指令流的序列，独立于第一电路的电源电压而向第二电路提供操作电压和至少一个低功率电压。 另一方面，提出了一种操作电源管理功能的方法。 该方法包括提供用于第一电路和第二电路的指令流，并响应于指令序列而独立于第一电路的电源电压而选择性地向第二电路提供操作电压和至少一个低功率电压 流。

公开(公告)号：US20160320826A1

公开(公告)日：2016-11-03

申请号：US14700017

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ali TAHA ,  Dexter Tamio CHUN

IPC: G06F1/32 ,  G06F12/02 ,  G11C14/00 ,  G11C7/10 ,  G11C11/406

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/205 ,  G11C11/406 ,  G11C14/0009 ,  G11C14/0054 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

Abstract translation: 提供了用于存储器功率降低的方法和装置。 该设备基于DRAM的功耗与DRAM中的数据相关联以及处理器中存储在DRAM中的数据的使用，确定在处理器的空闲状态期间是否将数据存储到DRAM或NVRAM中 关于由处理器使用存储在NVRAM中的数据以及与数据相关联的与第一功率状态和第二功率状态相关联的电流相关联的占空比，由NVRAM产生的功率消耗。 NVRAM是除闪存之外的一种非易失性随机存取存储器。 基于确定是否将数据存储在DRAM或NVRAM中，处理器将数据存储到DRAM或NVRAM之一中。