公开(公告)号：US20200280269A1

公开(公告)日：2020-09-03

申请号：US16645563

申请日：2018-10-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： HIDEYUKI ARAI ,  JUN'ICHI NAKA ,  TOSHIAKI OZEKI ,  KOJI OBATA

IPC: H02N2/18 ,  G01H11/08 ,  H01L41/04 ,  H01L41/08 ,  H01L41/113 ,  H01L41/193 ,  F16H19/00 ,  F16H19/06 ,  F16H19/04

Abstract: The present disclosure provides a vibration power generation device capable of generating large electric power relative to an amount of displacement of a portion of a specimen. Vibration power generation device according to the present invention includes piezoelectric part and displacement enhancer. In response to displacement of a portion of specimen, displacement enhancer displaces a portion of piezoelectric part by a displacement amount greater than an amount of the displacement of the portion of specimen. When the portion of piezoelectric part is displaced, piezoelectric part generates electric power in accordance with an amount of the displacement of the portion of piezoelectric part.

公开(公告)号：US20170310292A1

公开(公告)日：2017-10-26

申请号：US15465583

申请日：2017-03-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TOSHIAKI OZEKI ,  JUN'ICHI NAKA

IPC: H03F3/45 ,  H03F3/193

CPC classification number: H03F3/45251 ,  H03F3/193 ,  H03F3/45197 ,  H03F3/45659 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45082 ,  H03F2203/45352

Abstract: A differential amplifier circuit comprises: first and second input terminals; first and second output terminals; a first transistor comprising a gate terminal connected to the first input terminal; a second transistor comprising a gate terminal connected to the second input terminal; a first resistor connected between the source terminal of the first transistor and the source terminal of the second transistor; a third transistor comprising a drain terminal connected to the source terminal of the first transistor, a gate terminal connected to the drain terminal of the first transistor, and a source terminal connected to the first output terminal; a fourth transistor comprising a drain terminal connected to the source terminal of the second transistor, a gate terminal connected to the drain terminal of the second transistor, and a source terminal connected to the second output terminal; first to fourth current sources; and second and third resistors.

公开(公告)号：US20160329907A1

公开(公告)日：2016-11-10

申请号：US15089404

申请日：2016-04-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TAKUJI MIKI ,  JUNICHI NAKA ,  TOSHIAKI OZEKI

IPC: H03M1/12 ,  H03M1/08

CPC classification number: H03M1/1215 ,  H03M1/0836 ,  H03M1/1061

Abstract: A time-interleaved analog-to-digital (AD) converter includes: N AD converters; a frequency divider that receives a clock signal and applies 1/N frequency division N to the received clock signal to generate N frequency-divided clock signals to be supplied to the N AD converters; at least (N−1) variable delay circuit that adjusts delay time for at least (N−1) frequency-divided clock signal; a low pass filter circuit or an input buffer circuit that receives the clock signal and limits a frequency band of the received clock signal to generate a reference signal; and a control circuit that controls the delay time of the at least (N−1) variable delay circuit, and decreases one or more differences among digital output values output from the N AD converters when the reference signal is input to the N AD converters.

Abstract translation: 时间交织的模数（AD）转换器包括：N个AD转换器; 接收时钟信号并将1 / N分频N施加到所接收的时钟信号的分频器，以产生要提供给N AD转换器的N个分频时钟信号; 至少（N-1）个分频时钟信号的至少（N-1）个可变延迟电路，调整延迟时间; 低通滤波器电路或输入缓冲器电路，其接收时钟信号并限制所接收的时钟信号的频带以产生参考信号; 以及控制电路，其控制所述至少（N-1）个可变延迟电路的延迟时间，并且当所述参考信号被输入到所述N个AD转换器时，减小从所述N个AD转换器输出的数字输出值之间的一个或多个差异。

公开(公告)号：US20160329905A1

公开(公告)日：2016-11-10

申请号：US15131969

申请日：2016-04-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TOSHIAKI OZEKI ,  JUNICHI NAKA ,  TAKUJI MIKI

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/12

CPC classification number: H03M1/1009 ,  H03M1/0678 ,  H03M1/1004 ,  H03M1/1023 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/38

Abstract: An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N−1) first sampling circuits out of the execution of the calibration.

Abstract translation: A / D转换器包括：输入缓冲器; N个子A / D转换器，包括连接到输入缓冲器的N个第一采样电路，并且对相应采样槽中的输出模拟信号进行采样; 控制电路，一个接一个地执行N个第一采样电路的校准; 参考A / D转换器，包括连接到输入缓冲器的第二采样电路，并且在与N个第一采样之间执行校准的一个第一采样电路的采样时隙相同的采样时隙中对输出模拟信号进行采样 电路; 以及连接到输入缓冲器的第三采样电路，并且在与执行校准的第（N-1）个第一采样电路的采样时隙相同的采样时隙中对输出模拟信号进行采样。