公开(公告)号：US10210930B2

公开(公告)日：2019-02-19

申请号：US15219232

申请日：2016-07-25

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Masayoshi Nakayama ,  Yasuo Murakuki ,  Takafumi Maruyama

IPC分类号： G11C13/00 ,  G11C7/06 ,  G11C11/16 ,  G11C16/28

摘要： A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

公开(公告)号：US09747979B2

公开(公告)日：2017-08-29

申请号：US14826162

申请日：2015-08-13

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Masayoshi Nakayama ,  Kazuyuki Kouno ,  Reiji Mochida ,  Keita Takahashi

IPC分类号： G11C11/16 ,  G11C7/14 ,  G11C8/08 ,  G11C29/24 ,  G11C13/00 ,  H01L27/10 ,  H01L45/00 ,  H01L27/24 ,  G11C29/12

CPC分类号： G11C13/004 ,  G11C7/14 ,  G11C8/08 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/24 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2029/1202 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233

摘要： A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.

公开(公告)号：US09343115B2

公开(公告)日：2016-05-17

申请号：US14656689

申请日：2015-03-12

申请人： PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

发明人： Takanori Ueda ,  Kazuyuki Kouno ,  Yasuo Murakuki ,  Masayoshi Nakayama ,  Yuriko Ishitobi ,  Keita Takahashi

IPC分类号： G11C16/04 ,  G11C5/08 ,  G11C11/56 ,  G11C11/18 ,  G11C11/14 ,  G11C11/15 ,  G11C13/00 ,  G11C11/16 ,  G11C7/14

CPC分类号： G11C5/08 ,  G11C7/14 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/18 ,  G11C11/5607 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

摘要： A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.

摘要翻译： 存储器阵列包括具有串联连接的第一单元晶体管和电阻变化元件的电阻式存储单元阵列和具有串联连接的第二单元晶体管和电阻元件的参考单元阵列。 参考单元阵列的第二单元晶体管连接到参考源极线，并且电阻元件连接到参考位线。 虚拟存储单元连接到存储单元阵列中的参考位线，并且虚拟存储单元的电阻变化元件的两端通过参考位线短路。