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公开(公告)号：US20220057490A1
公开(公告)日：2022-02-24
申请号：US17486753
申请日：2021-09-27
Inventor： Motonori ISHII , Shigetaka KASUGA
IPC: G01S7/4861 , G01S17/10 , H04N5/225
Abstract: A driver circuit includes: a first node connected to a first signal line; a first switch transistor provided between a first power supply and a first capacitor; a second switch transistor provided between a second power supply and a second capacitor; a third switch transistor provided between the first capacitor and the first node; and a fourth switch transistor provided between the second capacitor and the first node.
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公开(公告)号：US20220003864A1
公开(公告)日：2022-01-06
申请号：US17481233
申请日：2021-09-21
Inventor： Yugo Nose , Shinzo KOYAMA , Akihiro ODAGAWA , Shigetaka KASUGA , Manabu USUDA
IPC: G01S17/08 , H01L31/107 , G01S7/48
Abstract: A distance measuring method according to the present disclosure includes: measuring, in an environment where background light is applied to an object, the illuminance of the background light; setting a distance measuring range based on the illuminance of the background light; setting, based on the distance measuring range set, an image capturing condition for an image capturer including a plurality of pixels each including an avalanche photo diode (APD) and an emission condition in which light is emitted from a light source; and measuring a distance to the object by controlling the image capturer and the light source based on the image capturing condition and the emission condition that are set.
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公开(公告)号：US20150103219A1
公开(公告)日：2015-04-16
申请号：US14578560
申请日：2014-12-22
Inventor： Shigetaka KASUGA , Motonori ISHII
IPC: H04N5/3745 , H04N5/378
CPC classification number: H04N5/3745 , H01L27/14643 , H04N5/363 , H04N5/378
Abstract: A pixel unit included in a sensor chip includes: a first pixel connected to a first feedback amplifier which is connected to a first column signal line as an input line and a first reset drain line as an output line; and a second pixel connected to a second feedback amplifier which is connected to a second column signal line as an input line and a second reset drain line as an output line. A drain of a reset transistor of the first pixel is connected to the first reset drain line, a drain of a reset transistor of the second pixel is connected to the second reset drain line, a source of an amplifying transistor of the first pixel is connected to the first column signal line, and a source of an amplifying transistor of the second pixel is connected to the second column signal line.
Abstract translation: 包括在传感器芯片中的像素单元包括：连接到第一反馈放大器的第一像素，其连接到作为输入线的第一列信号线和作为输出线的第一复位漏极线; 以及连接到第二反馈放大器的第二像素，其连接到作为输入线的第二列信号线和作为输出线的第二复位漏极线。 第一像素的复位晶体管的漏极连接到第一复位漏极线，第二像素的复位晶体管的漏极连接到第二复位漏极线，第一像素的放大晶体管的源极连接 到第一列信号线，并且第二像素的放大晶体管的源极连接到第二列信号线。
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公开(公告)号：US20230156370A1
公开(公告)日：2023-05-18
申请号：US18098451
申请日：2023-01-18
Inventor： Masaki TAMARU , Shigetaka KASUGA , Shinzo KOYAMA
IPC: H04N25/771 , H04N25/50 , H04N25/78
CPC classification number: H04N25/771 , H04N25/50 , H04N25/78
Abstract: A solid-state imaging apparatus includes a plurality of pixel circuits arranged in a matrix. Each pixel circuit includes: a photodiode; a first charge storage that stores a charge; a floating diffusion region that stores a charge; a second charge storage that stores a charge; a first transfer transistor that transfers a charge from the photodiode to the first charge storage; a second transfer transistor that transfers a charge from the first charge storage to the floating diffusion region; a first reset transistor that resets the floating diffusion region; and an accumulating transistor for accumulating a charge of the floating diffusion region in the second charge storage. The capacitance of the first charge storage is greater than the capacitance of the floating diffusion region, and the capacitance of the second charge storage is greater than the capacitance of the floating diffusion region.
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公开(公告)号：US20230131491A1
公开(公告)日：2023-04-27
申请号：US18069683
申请日：2022-12-21
Inventor： Shigetaka KASUGA , Masaki TAMARU , Yugo NOSE
IPC: H04N25/77 , G01S17/894 , G01S7/4863 , H04N25/78 , H04N25/703 , H04N13/254
Abstract: A solid-state imaging device includes: pixels; a first sample-and-hold circuit provided per column and generating a first differential voltage that is a difference between a first reset voltage and a first signal voltage output from a first pixel disposed in a corresponding column among the pixels; a second sample-and-hold circuit provided per column and generating a second differential voltage that is a difference between a second reset voltage and a second signal voltage output from a second pixel disposed in the corresponding column among the pixels and different from the first pixel; and an A/D conversion circuit provided per column and converting, into digital signals, a first voltage based on the first differential voltage output from the first sample-and-hold circuit disposed in the corresponding column and a second voltage based on the second differential voltage output from the second sample-and-hold circuit disposed in the corresponding column.
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Patent Agency Ranking
公开(公告)号：US20170187939A1
公开(公告)日：2017-06-29
申请号：US15461159
申请日：2017-03-16
Inventor： Shigetaka KASUGA , Seiji YAMAHIRA , Yoshihisa KATO
Abstract: A solid-state imaging device includes a detector, a count value storage, and a reader. The detector includes an avalanche amplification type light receiving element that detects a photon, and a resetter that resets an output potential of the light receiving element, and outputs a digital signal that indicates the presence or absence of incidence of a photon on the light receiving element. The count value storage performs counting by converting the digital signal output from the detector to an analog voltage, and stores the result of counting as a count value. The reader outputs an analog signal indicating the count value.
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公开(公告)号：US20230353906A1
公开(公告)日：2023-11-02
申请号：US18345805
申请日：2023-06-30
Inventor： Toru OKINO , Shinzo KOYAMA , Shigeru SAITOU , Masato TAKEMOTO , Masaki TAMARU , Hiroshi KOSHIDA , Shigetaka KASUGA , Yugo NOSE
IPC: H04N25/779 , H04N25/69
CPC classification number: H04N25/779 , H04N25/69
Abstract: Effective pixels and a failure detection pixel are connected to a control signal line for controlling an operation of the pixels and to an output signal line for outputting a result of failure detection in the pixels. Among the effective pixels, the effective pixels in a same row are connected in common to a same control signal line, and the effective pixels in a same column are connected in common to a same output signal line. The failure detection pixel is connected in common to at least one of the control signal line or the output signal line and configured to detect a failure in any of the effective pixels connected to the at least one of the control signal line or the output signal line.
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公开(公告)号：US20220191424A1
公开(公告)日：2022-06-16
申请号：US17683465
申请日：2022-03-01
Inventor： Shota YAMADA , Motonori ISHII , Shigetaka KASUGA , Masato TAKEMOTO , Yutaka HIROSE
IPC: H04N5/3745 , H04N5/357
Abstract: An imaging device includes: a solid-state imaging element having a plurality of pixel cells arranged in a matrix; and a signal processing part configured to process a detection signal outputted from each of the pixel cells. The pixel cells each include an avalanche photodiode and output a voltage corresponding to a count number of photons received by the avalanche photodiode as the detection signal. The signal processing part includes a variation calculation part configured to calculate a variation between the pixel cells in the detection signal outputted from each of the pixel cells, and a correction calculation part configured to correct the detection signal outputted from each of the pixel cells, on the basis of the variation calculated by the variation calculation part.
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公开(公告)号：US20220182572A1
公开(公告)日：2022-06-09
申请号：US17679942
申请日：2022-02-24
Inventor： Shota YAMADA , Shigetaka KASUGA , Motonori ISHII , Akito INOUE , Yutaka HIROSE
IPC: H04N5/3745 , G01S17/894 , G01S7/4865 , G01S7/481
Abstract: An imaging device includes: a solid-state imaging element having a plurality of pixel cells arranged in a matrix; and a control part configured to control the solid-state imaging element. The pixel cells each include an avalanche photodiode, a floating diffusion part configured to accumulate electric charges, a transfer transistor connecting a cathode of the avalanche photodiode and the floating diffusion part, and a reset transistor for resetting electric charges accumulated in the floating diffusion part. The control part controls the reset transistor to discharge electric charges exceeding a predetermined electric charge amount, of electric charges accumulated in the floating diffusion part from the cathode of the avalanche photodiode via the transfer transistor.
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公开(公告)号：US20220005855A1
公开(公告)日：2022-01-06
申请号：US17479846
申请日：2021-09-20
Inventor： Masaki TAMARU , Shigetaka KASUGA , Yusuke SAKATA , Mitsuyoshi MORI , Shinzo KOYAMA
IPC: H01L27/146
Abstract: A plurality of pixel cells are provided on a semiconductor substrate and arranged in a two-dimensional array. At least one of the plurality of pixel cells includes a light receiving part, a pixel circuit, and a second transistor. The light receiving part receives an incident light to generate an electrical charge. The pixel circuit includes first transistors arranged side by side along a first direction and a charge retention part that retains the electrical charge generated by the light receiving part. The pixel circuit outputs a light receiving signal in accordance with the electrical charge generated by the light receiving part. The second transistor connects the charge retention part to a memory part that stores the electrical charge. Seen along a thickness direction of the semiconductor substrate, the second transistor is apart from the first transistors in a second direction orthogonal to the first direction.
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