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    Memory with pattern oriented error correction code
    1.
    发明授权
    Memory with pattern oriented error correction code 有权

    公开(公告)号：US10289486B2

    公开(公告)日：2019-05-14

    申请号：US15649451

    申请日：2017-07-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hoon Ryu ,  Jong-Sik Na ,  TaeHyung Jung

    IPC: G06F11/10 ,  G11C29/52 ,  H03M13/19 ,  H03M13/29

    Abstract: Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data. A minimum distance of three in the disclosed ECC is maintained to make certain that a single bit is corrected on the read data to retrieve the originally stored memory data.

    MEMORY WITH PATTERN ORIENTED ERROR CORRECTION CODE
    2.
    发明申请
    MEMORY WITH PATTERN ORIENTED ERROR CORRECTION CODE 审中-公开

    公开(公告)号：US20190018732A1

    公开(公告)日：2019-01-17

    申请号：US15649451

    申请日：2017-07-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hoon Ryu ,  Jong-Sik Na ,  TaeHyung Jung

    IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  H03M13/19

    Abstract: Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data. A minimum distance of three in the disclosed ECC is maintained to make certain that a single bit is corrected on the read data to retrieve the originally stored memory data.

    Single bitline SRAM pixel and method for driving the same
    3.
    发明授权
    Single bitline SRAM pixel and method for driving the same 有权

    公开(公告)号：US12249299B2

    公开(公告)日：2025-03-11

    申请号：US17962956

    申请日：2022-10-10

    Applicant: OmniVision Technologies, Inc.

    Inventor： Qing Qin ,  Hoon Ryu

    IPC: G09G5/393 ,  G09G3/00 ,  G09G3/36 ,  G11C11/412 ,  G11C11/419 ,  H10B10/00

    Abstract: A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch includes an input and an output. The first switching transistor includes a first terminal, a second terminal, and a control terminal. The first switching transistor is operative to provide a conductive path and a non-conductive path between the bit line and the input of the latch responsive to a first control signal being asserted on the control terminal of the first switching transistor. The blocking transistor includes a control terminal and is operative to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line responsive to a second control signal. The blocking transistor facilitates the use of a single bit line.

    DRAM with simultaneous read and write for multiwafer image sensors
    6.
    发明授权
    DRAM with simultaneous read and write for multiwafer image sensors 有权

    公开(公告)号：US10672101B1

    公开(公告)日：2020-06-02

    申请号：US16292172

    申请日：2019-03-04

    Applicant: OmniVision Technologies, Inc.

    Inventor： Chia Ming Chen ,  Hoon Ryu ,  Qing Qin

    IPC: G06T1/60 ,  H04N5/335 ,  H04N5/374 ,  H04N5/378 ,  G06T5/50 ,  G06T5/00 ,  H04N5/30

    Abstract: A bond-per-pixel-block image sensor has a pixel array including multiple pixel blocks with selection circuitry to couple signals to an ADC. The image sensor has an image RAM of DRAM superblocks, each superblock with multiple DRAM blocks each having tristate output driving an image RAM output bus, and data input from several of the ADCs. Each DRAM block has an address multiplexor coupled to read and write addresses. DRAM blocks of each superblock are written simultaneously with data wider than a width of the image RAM output bus. A method of capturing and processing images includes reading a first image frame from pixels of a pixel block through ADCs; writing digital pixel data for the first image frame in a first DRAM superblock; and reading pixel data into an alignment buffer. The method includes overlapping reading the first image frame with writing a second image frame into a second superblock.

    Configurable interface alignment buffer between DRAM and logic unit for multiple-wafer image sensors
    7.
    发明授权
    Configurable interface alignment buffer between DRAM and logic unit for multiple-wafer image sensors 有权

    公开(公告)号：US10834352B2

    公开(公告)日：2020-11-10

    申请号：US16247475

    申请日：2019-01-14

    Applicant: OmniVision Technologies, Inc.

    Inventor： Qing Qin ,  Hoon Ryu ,  Taehyung Jung

    IPC: H04N5/378 ,  H04N5/374 ,  H04N5/369 ,  H04N5/3745 ,  H01L27/146

    Abstract: An image sensor has an array of pixels configured in multiple blocks; each block coupled to a separate analog-to-digital converter (ADC) to provide digitized image data. The ADCs feed digitized images into an image RAM; and the image RAM feeds digitized images to an alignment buffer in a first pixel order. The alignment buffer provides digitized images to an image processor in a second pixel order different from the first pixel order. In an embodiment, the alignment buffer uses a multiport RAM. In another embodiment, the alignment buffer uses first and second alignment buffer RAMs, writing one alignment buffer RAM while reading the other alignment buffer RAM to provide image data to the image processor. In embodiments, the alignment buffer provides digitized images in an order selectable between a full resolution and a reduced resolution order, and selectable between a right-to-left and left-to-right order.

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