公开(公告)号：US06809710B2

公开(公告)日：2004-10-26

申请号：US09765582

申请日：2001-01-22

申请人： Olivier F. Prache ,  Shashi D. Malaviya

发明人： Olivier F. Prache ,  Shashi D. Malaviya

IPC分类号： G09G332

CPC分类号： G09G3/3233 ,  G09G3/006 ,  G09G3/2014 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2300/0876 ,  G09G2310/0259 ,  G09G2310/066 ,  G09G2320/0214

摘要： A circuit is disclosed for driving an OLED in a graphics display. The circuit employs a current source operating in a switched mode. The output of the current source is connected to a terminal of the OLED. The current source is responsive to a combination of a selectively set cyclical voltage signal and a cyclical variable amplitude voltage signal. The current source, when switched on, is designed and optimized to supply the OLED with the amount of current necessary for the OLED to achieve maximum luminance. When switched off, the current source blocks the supply of current to the OLED, providing a uniform black level for an OLED display. The apparent luminance of the OLED is controlled by modulating the pulse width of the current supplied to the OLED, thus varying the length of time during which current is supplied to the OLED. By using a switched mode of operation at the current source, the circuit of the present invention is able to employ a larger range of voltages to control the luminance values in a current-driven OLED display.

摘要翻译： 公开了用于在图形显示器中驱动OLED的电路。 该电路采用以切换模式工作的电流源。 电流源的输出连接到OLED的端子。 电流源响应于选择性设置的周期性电压信号和循环可变幅度电压信号的组合。 电流源在接通时被设计和优化，以向OLED提供OLED达到最大亮度所需的电流量。 当关闭时，电流源阻止向OLED提供电流，为OLED显示器提供均匀的黑色电平。 通过调制提供给OLED的电流的脉冲宽度来控制OLED的表观亮度，从而改变向OLED提供电流的时间长度。 通过在电流源处使用开关操作模式，本发明的电路能够采用更大范围的电压来控制电流驱动OLED显示器中的亮度值。

公开(公告)号：US5243140A

公开(公告)日：1993-09-07

申请号：US771707

申请日：1991-10-04

申请人： Harsaran S. Bhatia ,  Mario J. Interrante ,  Suresh D. Kadakia ,  Shashi D. Malaviya ,  Mark H. McLeod ,  Sudipta K. Ray ,  Herbert I. Stoller

发明人： Harsaran S. Bhatia ,  Mario J. Interrante ,  Suresh D. Kadakia ,  Shashi D. Malaviya ,  Mark H. McLeod ,  Sudipta K. Ray ,  Herbert I. Stoller

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L23/5382 ,  H01L21/485 ,  H01L2224/16225 ,  H01L2924/19107

摘要： A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

公开(公告)号：US4608589A

公开(公告)日：1986-08-26

申请号：US499004

申请日：1983-07-11

申请人： George R. Goth ,  Ingrid E. Magdo ,  Shashi D. Malaviya

发明人： George R. Goth ,  Ingrid E. Magdo ,  Shashi D. Malaviya

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/60 ,  H01L29/41 ,  H01L29/72

CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L21/28 ,  H01L29/41

摘要： A self-aligned metal integrated circuit structure is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. The surface is planarized, leaving the structure of metal filling the regions between the pattern of dielectric material.

摘要翻译： 描述了自对准的金属集成电路结构，其实现了自对准的金属到硅接触和亚微米接触接触和金属到金属的间隔。 触点和金属之间的绝缘是具有一微米或更小的厚度尺寸的电介质材料的图案。 金属和电介质结构基本上是平面的。 形成该结构的方法包括提供硅体，然后在硅体的主表面上形成第一绝缘层。 在其上形成多晶硅层。 通过反应离子蚀刻在多晶硅层中形成开口，这导致结构具有基本水平的表面和基本垂直的表面。 然后在基本上水平的表面和基本垂直的表面上形成第二绝缘层。 该第二绝缘层的反应离子蚀刻基本上去除了水平层，并且在硅主体的主表面上提供了窄尺寸的区域的介电图案。 然后通过蚀刻去除剩余的多晶硅层，以在硅体的主表面上留下窄尺寸的区域。 导电层被毯子沉积在窄尺寸区域和其间的区域上。 表面被平坦化，留下金属的结构填充电介质材料图案之间的区域。

公开(公告)号：US4058808A

公开(公告)日：1977-11-15

申请号：US779668

申请日：1977-03-21

申请人： Shashi D. Malaviya

发明人： Shashi D. Malaviya

IPC分类号： H03M1/00 ,  H03K13/02

CPC分类号： H03M1/1019

摘要： An analog to digital converter suitable for fabrication according to integrated circuitry technology. The voltage to be converted is applied to a storage capacitor which is pulse discharged in discrete equal amounts determined by a voltage controlled constant current source. The pulses are counted and the total represents the input voltage. The current of the constant current source, and concomitantly the discrete pulsed discharge amounts, is varied during a calibrate mode depending upon any detected error. A known reference voltage is applied to the storage capacitor which is then pulsed down by the voltage controlled current source. Any deviation in the time of discharge, as compared to the known time (number of pulses) to discharge the capacitor, varies the voltage which controls the current magnitude of the constant current source.

摘要翻译： 适合根据集成电路技术制造的模数转换器。 要转换的电压被施加到由电压控制的恒定电流源确定的离散等量的脉冲放电的存储电容器。 脉冲被计数，总数代表输入电压。 根据任何检测到的误差，恒定电流源的电流以及伴随的离散脉冲放电量在校准模式期间是变化的。 将已知的参考电压施加到存储电容器，然后由电压控制的电流源将其降压。 与放电电容器的已知时间（脉冲数）相比，放电时间的任何偏差改变了控制恒流源的电流幅度的电压。

公开(公告)号：US4743781A

公开(公告)日：1988-05-10

申请号：US882058

申请日：1986-07-03

申请人： Harsaran S. Bhatia ,  Harry J. Jones ,  Shashi D. Malaviya

发明人： Harsaran S. Bhatia ,  Harry J. Jones ,  Shashi D. Malaviya

IPC分类号： H03K19/082 ,  H03K19/086 ,  H03K19/173 ,  H03K19/013 ,  H03K17/04 ,  H03K17/60

CPC分类号： H03K19/1738 ,  H03K19/086

摘要： A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs, while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors, the collector dotting of their respective reference transistors, the emitter dotting of one input transistor and a reference transistor to a constant current source, the emitter dotting of the other input transistor and the other reference transistor to a different constant current source, and an inhibit circuit for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.

摘要翻译： 用于集成电路芯片的新型点阵电路，提供线路切换，以及同时的真实和互补输出，同时不需要标准集电极电压钳位。 该电路由两个或多个输入晶体管的集电极点，其各自的参考晶体管的集电极点，一个输入晶体管的发射极点和参考晶体管连接到恒定电流源，另一个输入晶体管的发射极点 另一个参考晶体管连接到不同的恒流源，以及禁止电路，用于根据逻辑控制信号允许电流仅流向发射极点电路中的一个。

公开(公告)号：US4400865A

公开(公告)日：1983-08-30

申请号：US167184

申请日：1980-07-08

申请人： George R. Goth ,  Ingrid E. Magdo ,  Shashi D. Malaviya

发明人： George R. Goth ,  Ingrid E. Magdo ,  Shashi D. Malaviya

IPC分类号： H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/22

CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/28 ,  H01L29/41 ,  H01L2924/0002 ,  Y10S438/947

摘要： A self-aligned metal process is decribed which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. The surface is planarized leaving the structure of metal filling the regions between the pattern of dielectric material.

摘要翻译： 自对准金属工艺被描述，其实现了自对准金属与硅接触和亚微米接触接触和金属到金属的间隔。 触点和金属之间的绝缘是具有一微米或更小的厚度尺寸的电介质材料的图案。 金属和电介质结构基本上是平面的。 形成该结构的方法包括提供硅体，然后在硅体的主表面上形成第一绝缘层。 在其上形成多晶硅层。 通过反应离子蚀刻在多晶硅层中形成开口，这导致结构具有基本水平的表面和基本垂直的表面。 然后在基本上水平的表面和基本垂直的表面上形成第二绝缘层。 该第二绝缘层的反应离子蚀刻基本上去除了水平层，并且在硅主体的主表面上提供了窄尺寸的区域的介电图案。 然后通过蚀刻去除剩余的多晶硅层，以在硅体的主表面上留下窄尺寸的区域。 导电层被毯子沉积在窄尺寸区域和其间的区域上。 表面被平坦化，留下金属的结构填充介电材料图案之间的区域。

公开(公告)号：US4319148A

公开(公告)日：1982-03-09

申请号：US107810

申请日：1979-12-28

申请人： Shashi D. Malaviya

发明人： Shashi D. Malaviya

IPC分类号： H03K19/013 ,  H03K19/21

CPC分类号： H03K19/013 ,  H03K19/21

摘要： A 3-way Exclusive OR function is performed in an essentially single stage logic delay. A 3-way OR circuit produces a logical "1" output whenever at least one of three input operands is "1". A Two And Only Two logic circuit produces a logical "0" output when two and only two of the three input operands are "1". The outputs of the OR circuit and the Two And Only Two logic circuits are DOT-ANDed to provide a desired Exclusive OR function. In one form of the invention, the Two And Only Two logic circuit comprises three Schottky diode transistor NAND circuits each having two normal inputs and one inhibit input with the inhibit input of each of the three NAND circuits being connected to receive a different one of the three input operands while the two normal inputs being connected to receive the remaining ones of the three input operands. The OR circuit comprises four transistors having their emitters coupled to a common current source. The base of one of the four transistors is connected to a reference potential while the bases of the other three transistors are connected to receive respective one of the three input operands. Outputs of the three NAND circuits and the output of the 3-way OR circuit are DOT-ANDed at an input of an emitter follower output stage.

摘要翻译： 在基本单级逻辑延迟中执行3路异或运算。 只要三个输入操作数中的至少一个为“1”，三通OR电路就产生逻辑“1”输出。 只有两个逻辑电路当三个输入操作数中的两个和仅两个为“1”时，两个逻辑电路产生逻辑“0”输出。 OR电路和两个和两个逻辑电路的输出为DOT-AND，以提供所需的异或功能。 在本发明的一种形式中，两只和两只逻辑电路包括三个肖特基二极管晶体管NAND电路，每个具有两个正常输入和一个禁止输入，三个NAND电路中的每一个的禁止输入被连接以接收不同的一个 三个输入操作数，而两个正常输入被连接以接收三个输入操作数中的其余的输入操作数。 OR电路包括四个晶体管，其发射极耦合到公共电流源。 四个晶体管之一的基极连接到参考电位，而另外三个晶体管的基极连接以接收三个输入操作数中的相应一个。 在发射极跟随器输出级的输入端，三路NAND电路的输出和三路OR电路的输出为DOT-AND。

公开(公告)号：US06215840B1

公开(公告)日：2001-04-10

申请号：US09304259

申请日：1999-05-06

申请人： Shashi D. Malaviya ,  Olivier Prache

发明人： Shashi D. Malaviya ,  Olivier Prache

IPC分类号： G11C1928

CPC分类号： G11C8/04 ,  G11C19/184 ,  G11C19/28

摘要： Circuits for sequentially addressing memory locations in time with pulses received from a clock are disclosed. The circuits may provide a positive voltage output signal at successive output nodes associated with corresponding stages in the circuit responsive to the application of a clock signal to the circuit stages. The circuit may comprise at least first and second stages wherein said first stage comprises means for providing a positive voltage signal at a first output node in the first stage in response to application of a first positive clock pulse to the first stage, and wherein said second stage comprises means for providing a positive voltage signal at a second output node in the second stage in response to application of a second positive clock pulse to the second stage. Addressing of memory locations that contain pixel information for a video display is one particular application in which sequential addressing may be required. Sequential addressing is useful in video applications because it permits sequential selection of the pixel rows and columns that make up the display screen. Sequential scanning of the memory locations for screen information can be carried out in conjunction with the scanning of an electron source across the screen of the display.

摘要翻译： 公开了用于从时钟接收的脉冲随时间地寻址存储器位置的电路​​。 电路可以响应于将时钟信号施加到电路级而在与电路中的相应级相关联的连续输出节点处提供正电压输出信号。 电路可以包括至少第一和第二级，其中所述第一级包括用于响应于向第一级施加第一正时钟脉冲而在第一级中的第一输出节点处提供正电压信号的装置，并且其中所述第二级 响应于向第二级施加第二正时钟脉冲，在第二级中的第二输出节点处提供正电压信号的装置。 包含视频显示的像素信息的存储器位置的寻址是可能需要顺序寻址的一个特定应用。 顺序寻址在视频应用中非常有用，因为它允许顺序选择组成显示屏的像素行和列。 可以结合扫描显示器屏幕上的电子源来执行屏幕信息的存储单元的连续扫描。

公开(公告)号：US4764799A

公开(公告)日：1988-08-16

申请号：US904430

申请日：1986-10-27

申请人： Shashi D. Malaviya

发明人： Shashi D. Malaviya

IPC分类号： H01L21/308 ,  H01L29/06 ,  H01L27/12

CPC分类号： H01L21/3085 ,  H01L21/3086 ,  H01L29/0657

摘要： Disclosed is a submicron wide single crystal silicon structure protruding from a monolithic silicon body. This three-dimensional structure includes lower section of a first (N) conductivity type and an upper section of a second (P) conductivity type. The upper section consisting of narrow top and bottom portions separated by a relatively wide middle portion, constitutes the silicon material from which various active or passive integrated circuit devices may be fabricated. For example, in the case of an NPN transistor, the central region of the middle portion constitutes the base region, the emitter and collector being embedded in the two outer side regions thereof in a mutually facing relationship. Electrical contacts to the elements of the IC device are established on the top and/or sides of the protruding structure. Owing to its free-standing self-isolated characteristic, dielectric isolation of the IC device is not necessary. Alternatively, total dielectric isolation of the IC may be achieved by utilizing a dielectric material for the bottom of the protrusion.

摘要翻译： 公开了从单片硅体突出的亚微米宽的单晶硅结构。 该三维结构包括第一（N）导电类型的下部和第二（P）导电类型的上部。 由较窄的顶部和底部由较宽的中间部分分开的上部构成硅材料，可从中制造各种有源或无源集成电路器件。 例如，在NPN晶体管的情况下，中间部分的中心区域构成基极区域，发射极和集电体以相互面对的关系嵌入其两个外侧区域。 在突出结构的顶部和/或侧面上建立与IC器件元件的电接触。 由于其独立的自隔离特性，IC器件的绝缘隔离是不必要的。 或者，可以通过利用用于突起的底部的介电材料来实现IC的全介电隔离。

公开(公告)号：US4739252A

公开(公告)日：1988-04-19

申请号：US855241

申请日：1986-04-24

申请人： Shashi D. Malaviya ,  Daniel P. Morris

发明人： Shashi D. Malaviya ,  Daniel P. Morris

IPC分类号： G01R15/00 ,  G01R19/00 ,  G01R19/165 ,  G01R31/26 ,  G01R31/02

CPC分类号： G01R31/2632 ,  G01R19/0092

摘要： An attenuator useful in measuring low level leakage currents is disclosed. The attenuator includes a plurality of current dividers coupled in cascade. Each current divider includes an input and two outputs between which the current entering the input is divided. The current exiting the last divider is significantly attenuated from that entering the attenuator. The attenuator output is coupled to the device under test and to one input of a differential amplifier. A known current is input to the differential amplifier and part is directed to the attenuator input and the other part to a current measuring device. The difference between the known current input to the differential amplifier and that measured is the current input to the attenuator. In the steady state, the current input to the differential amplifier from the current attenuator is about zero. Accordingly, the leakage current is equal to the known current entering the differential amplifier less the measured current divided by m, the attenuation provided by the attenuator.