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公开(公告)号：US07812374B2
公开(公告)日：2010-10-12
申请号：US11819369
申请日：2007-06-27
申请人： Nobuyuki Tamura , Ken Suzuki , Katsuhiro Ootani
发明人： Nobuyuki Tamura , Ken Suzuki , Katsuhiro Ootani
IPC分类号： H01L29/772
CPC分类号： H01L21/823807 , H01L29/7843 , Y10S438/938
摘要： A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction; and a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction, wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film.
摘要翻译： 半导体器件包括在半导体衬底的第一有源区上的第一MIS晶体管，第一MIS晶体管包括：设置在第一有源区上的第一栅极绝缘膜; 设置在所述第一栅极绝缘膜上的第一栅电极; 第一应力绝缘膜，设置在上表面和面对第一栅电极的栅极长度方向的侧面，使得第一应力作用在栅极长度方向上的第一MIS晶体管的沟道上; 以及第一基极绝缘膜，其设置在所述第一栅电极的面对栅极宽度方向的侧面上，其中所述第一栅电极的面对栅极宽度方向的侧面未被所述第一应力绝缘膜覆盖。
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公开(公告)号：US20080093673A1
公开(公告)日：2008-04-24
申请号：US11819369
申请日：2007-06-27
申请人： Nobuyuki Tamura , Ken Suzuki , Katsuhiro Ootani
发明人： Nobuyuki Tamura , Ken Suzuki , Katsuhiro Ootani
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L21/823807 , H01L29/7843 , Y10S438/938
摘要： A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction; and a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction, wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film.
摘要翻译： 半导体器件包括在半导体衬底的第一有源区上的第一MIS晶体管，第一MIS晶体管包括：设置在第一有源区上的第一栅极绝缘膜; 设置在所述第一栅极绝缘膜上的第一栅电极; 第一应力绝缘膜，设置在上表面和面对第一栅电极的栅极长度方向的侧面，使得第一应力作用在栅极长度方向上的第一MIS晶体管的沟道上; 以及第一基极绝缘膜，其设置在所述第一栅电极的面对栅极宽度方向的侧面上，其中所述第一栅电极的面对栅极宽度方向的侧面未被所述第一应力绝缘膜覆盖。
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公开(公告)号：US20080077378A1
公开(公告)日：2008-03-27
申请号：US11822781
申请日：2007-07-10
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
摘要翻译： 电路模拟装置具有获取关于晶体管的数据的模块，用于产生表示由隔离区域引起的晶体管有源区上的应力的影响的模型参数的模型参数生成单元，以及用于评估晶体管的特性的模拟执行单元 使用与模型参数相关联的模拟程序。 模型参数包括关于晶体管有源区的宽度的术语，关于外围有源区的宽度的术语，以及关于晶体管有源区和外围有源区之间的宽度的项。
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4.发明申请Method for designing semiconductor integrated circuit and method of circuit simulation 审中-公开半导体集成电路设计方法及电路仿真方法公开(公告)号：US20080021689A1
公开(公告)日：2008-01-24
申请号：US11812705
申请日：2007-06-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5036
摘要： By using, as a model expression, an expression showing an inverse proportion between a change rate ΔIdsat/Idsat of saturated current value and a product of a gate protrusion length E1 and a gate width Wg of a transistor and a coefficient, modeling is executed for a transistor property that depends on the gate protrusion length. This provides a circuit simulation that takes into consideration the gate protrusion length of a gate electrode.
摘要翻译： 通过使用作为模型表达式，表示在饱和电流值的变化率DeltaIdsat / Idsat与栅极突起长度E 1与晶体管的栅极宽度Wg的乘积与系数之间成反比的表达式，进行建模 对于取决于栅极突起长度的晶体管性质。 这提供了考虑栅电极的栅极突起长度的电路模拟。
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公开(公告)号：US20070018209A1
公开(公告)日：2007-01-25
申请号：US11410063
申请日：2006-04-25
申请人： Yasuyuki Sahara , Katsuhiro Ootani
发明人： Yasuyuki Sahara , Katsuhiro Ootani
CPC分类号： H01L27/092 , G06F17/5036 , H01L27/0207
摘要： A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at one end thereof to a first gate wiring and includes at the other end thereof a first protruding portion protruding at a side opposite to the first gate wiring side from the first active region A first NMIS transistor includes a second active region which is formed on the semiconductor substrate with a space left from the first active region and a second gate electrode which is formed on the second active region and which is connected at one end thereof to the first gate wiring and includes at the other end thereof a second protruding portion protruding at a side opposite to the first gate wiring side from the second active region. A protruding length of the first protruding portion of the first PMIS transistor is greater than a protruding length of the second protruding portion of the first NMIS transistor.
摘要翻译： 第一PMIS晶体管包括形成在半导体衬底上的第一有源区和形成在第一有源区上的第一栅电极，该第一有源区的一端连接到第一栅极布线，另一端包括 第一突出部分在与第一有源区域A的第一栅极布线侧相对的一侧突出。第一NMIS晶体管包括形成在半导体衬底上的具有从第一有源区域剩下的空间的第二有源区和第二栅电极， 形成在所述第二有源区上，并且在其一端连接到所述第一栅极布线，并且在其另一端包括在与所述第二有源区的所述第一栅极布线侧相对的一侧突出的第二突出部。 第一PMIS晶体管的第一突出部分的突出长度大于第一NMIS晶体管的第二突出部分的突出长度。
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公开(公告)号：US07476957B2
公开(公告)日：2009-01-13
申请号：US11979669
申请日：2007-11-07
IPC分类号： H01L21/26
CPC分类号： H01L27/0207 , H01L21/82385 , H01L21/823892 , H01L27/0922
摘要： An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.
摘要翻译： 集成电路包括：第一导电类型的第一阱; 第二导电类型的第二阱在沿栅极长度方向延伸的阱边界处与第一阱接触; 第一晶体管，具有设置在第一阱中的第二导电类型的第一有源区; 以及第二晶体管，其具有设置在第一阱中的第二导电类型的第二有源区，并且与栅极宽度方向上的第一有源区的长度不同。 第一有源区域在栅极宽度方向上的中心位置与第二有源区域相对于阱边界在栅极宽度方向上的中心位置对准。
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公开(公告)号：US20060180865A1
公开(公告)日：2006-08-17
申请号：US11401400
申请日：2006-04-11
申请人： Toshihiro Kogami , Katsuhiro Ootani , Katsuya Arai
发明人： Toshihiro Kogami , Katsuhiro Ootani , Katsuya Arai
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L29/41725
摘要： An electrostatic discharge protected transistor of the present invention includes transistors in an active region composed of a p-type semiconductor substrate and surrounded by element isolation regions. On the active region composed of the p-type semiconductor substrate, an on-source silicide film and an on-drain silicide film are provided. The on-drain silicide film is not provided in a portion located on a boundary of each transistor and divided to correspond to the respective transistors. As a result, regions between respective pairs of the transistors have high resistances, and it is, therefore, possible to prevent a current from flowing between the different transistors and prevent local current concentration. It is thereby possible to allow the electrostatic discharge protected transistor to make most use of an electrostatic destruction protection capability per unit area without increasing an area of the transistor.
摘要翻译： 本发明的静电放电保护晶体管包括由p型半导体衬底构成并由元件隔离区包围的有源区中的晶体管。 在由p型半导体衬底构成的有源区上，提供源极硅化物膜和漏极硅化物膜。 漏极硅化物膜不设置在位于每个晶体管的边界上的部分中，并且被分隔以对应于各个晶体管。 结果，各对晶体管之间的区域具有高电阻，因此可以防止电流在不同的晶体管之间流动并且防止局部电流集中。 因此，可以使静电放电保护晶体管最大程度地利用每单位面积的静电破坏保护能力，而不增加晶体管的面积。
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公开(公告)号：US07093215B2
公开(公告)日：2006-08-15
申请号：US10751892
申请日：2004-01-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H01L27/0207
摘要： An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.
摘要翻译： 本发明的半导体电路器件包括N阱和P阱。 N阱具有被沟槽隔离环绕的PMIS有源区，并且P阱具有由沟槽隔离包围的NMIS有源区。 PMIS有源区域各自设置有P沟道晶体管的栅极，并且NMIS有源区域各自设置有N沟道晶体管的栅极。 设计布局，使得NMIS有效区域与Y方向上的PMIS有效区域之间的距离Dpn基本上变为固定值。 因此，从沟槽隔离施加到栅极下方的沟道区的沟槽隔离应力对于各个晶体管而变得均匀，导致电路仿真精度的提高。
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9.发明授权Power circuit including inrush current limiter, and integrated circuit including the power circuit 有权包括浪涌电流限制器的电源电路和包括电源电路的集成电路
公开(公告)号：US6150800A
公开(公告)日：2000-11-21
申请号：US395971
申请日：1999-09-15
申请人： Masayoshi Kinoshita , Shiro Sakiyama , Jun Kajiwara , Katsuji Satomi , Hiroo Yamamoto , Katsuhiro Ootani
发明人： Masayoshi Kinoshita , Shiro Sakiyama , Jun Kajiwara , Katsuji Satomi , Hiroo Yamamoto , Katsuhiro Ootani
CPC分类号： G05F1/573 , G05F1/575 , Y10S323/908
摘要： A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source. Accordingly, during the initial operation of the power circuit, the gate potential of the limiting transistor gradually decreases while the gate-source voltage of the output transistor gradually increases. As a result, the generation of the inrush current can be suppressed.
摘要翻译： 描述了一种电源电路，其包括用于在电源电路的初始操作期间防止产生浪涌电流的装置，而不增加电源电路的尺寸。 电源电路包括用于从电源向输出端子提供电流的输出晶体管，以及差分放大器，用于根据预设的方式控制由输出晶体管提供的电流，以调节输出端子处的电压 参考电压。 在差分放大器的输出级的电流路径上提供限制晶体管作为源极跟随器。 使用限制晶体管的源极电位来控制输出晶体管的栅极电位。 在电源电路开始工作之前，操作控制器对电容器充电以控制限流晶体管的栅极电位，使得在电源电路的初始操作期间，通过使用电流源来放电电容器。 因此，在电源电路的初始动作期间，限制晶体管的栅极电位逐渐降低，同时输出晶体管的栅极 - 源极电压逐渐增大。 结果，可以抑制浪涌电流的产生。
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公开(公告)号：US07709900B2
公开(公告)日：2010-05-04
申请号：US11892053
申请日：2007-08-20
IPC分类号： H01L23/62
CPC分类号： H01L21/76895 , H01L21/823475 , H01L27/0207
摘要： A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
摘要翻译： 半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。
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