发明授权
- 专利标题: Semiconductor circuit device and circuit simulation method for the same
- 专利标题(中): 半导体电路器件和电路仿真方法相同
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申请号: US10751892申请日: 2004-01-07
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公开(公告)号: US07093215B2公开(公告)日: 2006-08-15
- 发明人: Yasuyuki Sahara , Katsuhiro Ootani , Kazuhisa Nakata , Shinsaku Sekido
- 申请人: Yasuyuki Sahara , Katsuhiro Ootani , Kazuhisa Nakata , Shinsaku Sekido
- 申请人地址: JP Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JP Osaka
- 代理机构: McDermott Will & Emery LLP
- 优先权: JP2003-027890 20030205
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.
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