公开(公告)号：US06708026B1

公开(公告)日：2004-03-16

申请号：US09481248

申请日：2000-01-11

申请人： Nikolaus Klemmer ,  Antonio J. Montalvo ,  Steven L. White

发明人： Nikolaus Klemmer ,  Antonio J. Montalvo ,  Steven L. White

IPC分类号： H04B126

CPC分类号： H03L7/1976 ,  H03D7/163

摘要： A programmable digital divider operates under the control of a division controller to derive a second synthesized frequency based on a first synthesized frequency. The programmable divider divides the first synthesized signal to derive the second synthesized signal. The division amount is an integer, but varies between integer values if necessary to achieve a non-integer average division value. The majority of the noise generated by the frequency synthesizer is generated away from the centerline frequency and is easily filtered by narrowband filter. The frequency synthesizer may optionally be incorporated into a modified phase-locked loop to generate the second synthesized signal. By using a digital divider, instead of a traditional phase-locked loop, these embodiments allow for integration of the frequency synthesizer onto an integrated circuit, thereby lowering cost and improving resistance to noise spurs. This approach is particularly suited to telecommunications applications.

摘要翻译： 可编程数字分频器在分频控制器的控制下操作，以基于第一合成频率导出第二合成频率。 可编程分频器分割第一合成信号以导出第二合成信号。 分割量是一个整数，但如果需要，可以在整数值之间变化，以获得非整数平均除法值。 由频率合成器产生的大部分噪声是从中心线频率产生的，并且容易被窄带滤波器滤波。 频率合成器可以可选地并入修改的锁相环以产生第二合成信号。 通过使用数字分频器而不是传统的锁相环，这些实施例允许将频率合成器集成到集成电路上，从而降低成本并提高对噪声的抵抗力。 这种方法特别适用于电信应用。

公开(公告)号：US06265947B1

公开(公告)日：2001-07-24

申请号：US09481461

申请日：2000-01-11

申请人： Nikolaus Klemmer ,  Steven L. White

发明人： Nikolaus Klemmer ,  Steven L. White

IPC分类号： H03L7095

CPC分类号： H03L7/14 ,  H03L7/0802 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/18 ,  H04W52/028 ,  Y02D70/122

摘要： A power conserving phase-locked loop achieves power savings by adding a switch which selectively enables the bias current for the charge pump associated with the phase comparator of the phase-locked loop. The switch is connected by a logic circuit to a counter that tracks the expected arrival time of a signal edge of the reference signal. Immediately prior to the arrival of the expected signal edge, the switch is enabled, thereby creating and applying the bias current to activate the charge pump in the event that a correction is needed to maintain the “lock” in the phase-locked loop. When the signal edge passes, the bias current is turned off again before the arrival of the next signal edge. This switching may result in a ten percent duty cycle in the biasing current, resulting in approximately a ninety percent power savings. The phase-locked loop may be used for a variety of applications, such as a frequency synthesizer in a receiver chain of wireless communications mobile terminals, where power consumption is a concern.

摘要翻译： 省电锁相环通过添加一个开关来实现功率节省，该开关选择性地启用与锁相环相位比较器相关联的电荷泵的偏置电流。 开关由逻辑电路连接到跟踪参考信号的信号边缘的预期到达时间的计数器。 在预期信号边缘到达之前，开关被使能，从而在需要进行校正以维持锁相环中的“锁定”的情况下，产生和施加偏置电流来激活电荷泵。 当信号边沿通过时，偏置电流在下一个信号边缘到达之前被再次关断。 这种切换可能导致偏置电流占用10％的周期，导致大约90％的功率节省。 锁相环可以用于各种应用，例如无线通信移动终端的接收机链中的频率合成器，其中功耗是关注的。

公开(公告)号：US06265902B1

公开(公告)日：2001-07-24

申请号：US09432897

申请日：1999-11-02

申请人： Nikolaus Klemmer ,  Steven L. White

发明人： Nikolaus Klemmer ,  Steven L. White

IPC分类号： H03D300

CPC分类号： H03L7/0891 ,  H03D13/004 ,  H03L7/183

摘要： An improved digital phase detector is provided for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge. The digital phase detector includes a detector circuit for detecting a cycle slip where two successive leading edges of one of the reference and frequency source signals are received before a leading edge of the other signal is received. An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to said detecting.

摘要翻译： 提供了一种改进的数字相位检测器，用于检测和补偿参考信号和频率源信号之间的循环滑移，每个参考和频率源信号包括脉冲，每个脉冲由前沿和后沿定义。 数字相位检测器包括检测器电路，用于检测在接收另一信号的前沿之前接收到参考和频率源信号之一的两个连续前沿的周期滑移。 输出电路可操作地耦合到检测器电路，用于响应于所述检测而形成校正信号。

公开(公告)号：US06477196B1

公开(公告)日：2002-11-05

申请号：US09386039

申请日：1999-08-30

申请人： Christopher J. Swanke ,  Steven L. White

发明人： Christopher J. Swanke ,  Steven L. White

IPC分类号： H04L2726

CPC分类号： H04B1/7102

摘要： A method of excising one or more narrow-band interfering signals in a direct sequence spread spectrum receiver that performs a magnitude spectral analysis on baseband signals in a detection channel to determine which frequency bins in the spectral analysis output contain the interfering narrow-band signals by comparing the magnitude of the signals in the frequency bins to a threshold. The corrupted frequency bins are determined by the signal magnitudes exceeding the threshold and band reject filters excise the narrow-band signals in the signal channel in accordance with the corrupted frequency bins.

摘要翻译： 一种在直接序列扩频接收机中切除一个或多个窄带干扰信号的方法，该接收机对检测信道中的基带信号执行幅度谱分析，以确定频谱分析输出中的哪些频率包含干扰窄带信号 将频率仓中的信号的幅度与阈值进行比较。 损坏的频率仓由超过阈值的信号幅度确定，并且带阻滤波器根据损坏的频率仓对信号通道中的窄带信号进行消除。

公开(公告)号：US5003639A

公开(公告)日：1991-04-02

申请号：US438244

申请日：1989-11-20

申请人： Steven L. White

发明人： Steven L. White

IPC分类号： A42B1/18 ,  A42B1/24

CPC分类号： A42B1/18 ,  A42B1/24

摘要： The invention relates to a protector for cap visors consisting of a flexible sheet of soil resistant or washable material having ends and lateral sides which is folded over the visor periphery and the material includes fastening cords attached to clips which are releasably affixed to the edges of the visor adjacent the cap headband. The protective device covers the majority of the visor and by the use of colors, decorations or advertising the protector ascetically adds to the cap appearance.

摘要翻译： 本发明涉及一种用于遮盖罩的保护器，其由具有端部和侧面的柔性片材的抗污性或可洗涤材料组成，折叠在遮阳板周边上，并且材料包括附接到夹子的紧固绳索，该夹子可释放地固定到 遮阳板靠近帽头带。 保护装置覆盖了大多数的遮阳板，并且通过使用颜色，装饰品或广告，保护器可以增加帽子的外观。

公开(公告)号：US06968021B1

公开(公告)日：2005-11-22

申请号：US09961666

申请日：2001-09-24

申请人： Steven L. White ,  Joseph C. Whited ,  Thomas L. Tapp ,  Rodney L. Mickelson

发明人： Steven L. White ,  Joseph C. Whited ,  Thomas L. Tapp ,  Rodney L. Mickelson

IPC分类号： H03D1/00 ,  H04L1/00 ,  H04L7/00 ,  H04L7/02 ,  H04L25/03 ,  H04L27/00

CPC分类号： H04L1/005 ,  H04L1/0054 ,  H04L1/0055 ,  H04L1/0065 ,  H04L1/0071 ,  H04L7/0062 ,  H04L25/03171 ,  H04L25/03197 ,  H04L2025/03407 ,  H04L2027/0048

摘要： A bandwidth efficient advanced modulation waveform modem using concatenated iterative turbo coding and continuous phase modulation is disclosed. A demodulator in the modem has a turbo decoder and a decision feedback carrier and time tracking algorithm to track a carrier and adjust timing. The decision feedback carrier and time tracking algorithm may use an APP decoder as a decision device to provide symbol decisions at a high error rate and low latency for a coded input data stream. A symbol phase estimator produces a symbol phase error estimate from the symbol decisions. An erasure decision function decides which symbol decisions are correct and which symbol decisions are erasures. A carrier tracking function receives the symbol phase error estimates when the symbol decisions are correct and receives erasure inputs when the symbol decisions are erasures to maintain carrier tracking.

摘要翻译： 公开了一种使用级联迭代turbo编码和连续相位调制的带宽高效调制波形调制解调器。 调制解调器中的解调器具有turbo解码器和用于跟踪载波并调整定时的判定反馈载波和时间跟踪算法。 判定反馈载波和时间跟踪算法可以使用APP解码器作为决策设备，以便以高错误率和低延迟为编码的输入数据流提供符号决定。 符号相位估计器从符号判定产生符号相位误差估计。 擦除决策功能决定哪些符号决定是正确的，哪些符号决定是擦除。 当符号判定是正确的时候，载波跟踪功能接收符号相位误差估计，并且当符号决定是擦除以维持载波跟踪时接收擦除输入。

公开(公告)号：US07266161B1

公开(公告)日：2007-09-04

申请号：US10606724

申请日：2003-06-26

申请人： Billy D. Hart ,  Steven L. White

发明人： Billy D. Hart ,  Steven L. White

IPC分类号： H03D3/00

CPC分类号： H03D3/006

摘要： An apparatus and method provides efficient parallel processing for use with a single-bit sampler that provides single-bit samples at a high sample rate. A serial-to-parallel converter converts the single-bit samples into parallel single-bit samples at a reduced sample rate. A digital quadrature mix performs a frequency shift to the parallel single-bit samples and simultaneously performs a real-to-complex conversion of the parallel single-bit samples from the serial-to-parallel converter to provide parallel I and Q output values at an intermediate frequency. The serial-to-parallel converter has shift register stages that provide a memory for use in functional realization of a boxcar filter and decimation-by-two in the digital quadrature mix. The digital quadrature mix utilizes logic to route and invert the parallel single-bit samples resulting in the parallel I and Q single-bit output values. Additional filter and decimate stages may be used to process the parallel I and Q single-bit output values.

摘要翻译： 一种装置和方法提供了与单位采样器一起使用的高效并行处理，该采样器以高采样率提供单位采样。 串并转换器以降低的采样率将单位采样转换为并行单位采样。 数字正交混合器对并行单比特采样进行频移，并且同时对串并转换器的并行单比特采样进行实 - 复转换，从而提供并行I和Q输出值 中频。 串并转换器具有移位寄存器级，其提供用于盒式滤波器的功能实现的存储器，并且在数字正交混合中逐个抽取。 数字正交混合使用逻辑来对并行单位采样进行路由和反相，产生并行I和Q单位输出值。 附加的滤波器和抽取级可用于处理并行I和Q单位输出值。

公开(公告)号：US07088793B1

公开(公告)日：2006-08-08

申请号：US10124798

申请日：2002-04-17

申请人： Rodney L. Mickelson ,  Thomas L. Tapp ,  Steven L. White

发明人： Rodney L. Mickelson ,  Thomas L. Tapp ,  Steven L. White

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H04L25/03171 ,  H04L1/005 ,  H04L1/0066

摘要： An equalizer is used with complex modulation modems to reduce intersymbol interference. The equalizer includes an equalizer filter that receives an input data signal and adapts to compensate for the noisy communications channels to reduce intersymbol interference to the input signal. A branch metric computer demodulates the equalizer filter adapted input data signal. A decision device delivers an alpha value, starting phase information and confidence values from the demodulated input data signal. A gain determination function receives the confidence values and determines adaptation gain for the equalizer filter. A remodulator receives the alpha value and starting phase information and remodulates the alpha value and starting phase information into a remodulated data signal. A summing function compares the remodulated data signal to a delayed version of the input signal to generate an error signal for the equalizer filter to adjust the equalizer filter.

摘要翻译： 均衡器与复数调制调制解调器一起使用以减少符号间干扰。 均衡器包括均衡器滤波器，其接收输入数据信号并适于补偿有噪声的通信信道以减少对输入信号的符号间干扰。 分支度量计算机解调均衡器滤波器适配输入数据信号。 判定装置传送α值，从解调输入数据信号开始相位信息和置信度值。 增益确定功能接收置信度值并确定均衡器滤波器的自适应增益。 重新调制器接收α值和起始相位信息，并重新调制α值并将起始相位信息重新调入数据信号。 求和功能将再调制的数据信号与输入信号的延迟版本进行比较，以产生用于均衡器滤波器的误差信号，以调整均衡器滤波器。

公开(公告)号：US06208212B1

公开(公告)日：2001-03-27

申请号：US09266317

申请日：1999-03-11

申请人： Steven L. White

发明人： Steven L. White

IPC分类号： H03B2700

CPC分类号： H03K3/0322 ,  H03K3/0231 ,  H03K3/03 ,  H03K5/133 ,  H03K2005/00176

摘要： A delay cell comprises a fast delay stage including a differential amplifier for connection to a differential input. A slow delay stage includes a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage. An output circuit is connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current.

摘要翻译： 延迟单元包括快速延迟级，其包括用于连接到差分输入的差分放大器。 缓慢延迟级包括与快速延迟级差分放大器并联连接并具有用于设置延迟量的电容装置的差分放大器。 电流源产生偏置电流。 电流开关连接在电流源和快速延迟级之间，缓慢的延迟级可在快速延迟级与慢速延迟级之间切换偏置电流。 输出电路连接到快速和慢速延迟级，用于响应于快速延迟级电流和慢延迟级电流之间的比率而形成相对于差分输入延迟的差分输出。

公开(公告)号：US08191175B1

公开(公告)日：2012-06-05

申请号：US12505186

申请日：2009-07-17

申请人： Steven L. White

发明人： Steven L. White

IPC分类号： A42B1/00

CPC分类号： A42B1/062 ,  A42B1/18

摘要： A visor protector for caps having a visor including a periphery having a front edge, a pair of lateral edges, and upper and lower sides. The visor protector includes a flexible body having an upper portion and a lower portion. The upper portion of the flexible body meets the lower portion of the flexible body at a leading edge of the flexible body. The upper portion of the flexible body is receivable on the upper side of the visor, and the lower portion of the flexible body is receivable on the lower side of the visor. The upper and lower portions of the flexible body cooperate to define a substantial U-shape, wherein the visor is receivable between the upper and lower portions such that the leading edge of the flexible body is substantially aligned with the front edge of the visor. The visor protector includes a pair of spring clips that each have a first leg that is engageable with the upper portion of the flexible body and a second leg that is engageable with the lower portion of the flexible body. The spring clips are configured to urge the flexible body into engagement with the visor. Indicia, such as advertising, can be placed on the visor protector to provide the perfect promotional platform for products.

摘要翻译： 一种具有遮阳板的遮阳板护罩，其具有包括前边缘，一对侧边缘以及上侧和下侧的周边的遮阳板。 遮阳板保护器包括具有上部和下部的柔性主体。 柔性体的上部在柔性体的前缘处与柔性体的下部相交。 柔性体的上部可接收在遮阳板的上侧，柔性体的下部可接收在遮阳板的下侧。 柔性体的上部和下部配合以限定大致的U形，其中遮阳板可接纳在上部和下部之间，使得柔性体的前缘基本上与遮阳板的前边缘对准。 遮阳板保护器包括一对弹簧夹，每个弹簧夹具有可与柔性体的上部接合的第一腿部和可与柔性体的下部接合的第二腿部。 弹簧夹构造成促使柔性体与遮阳板接合。 标贴，如广告，可以放在护目镜上，为产品提供完美的促销平台。