摘要:
A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector signals (UP/DN) dependent on the sign of the phase difference; and a charge pump (61) comprising current generating means and controlled switches (64, 65) arranged to convert pulses on the detector signals to current pulses from a reference voltage (Vdd′) to a common terminal (Vloop) connected to the loop filter or to current pulses from the common terminal to ground. The current generating means comprises at least one resistor (62, 63) connected between the common terminal and the switches, and the charge pump comprises an operational amplifier (66) coupled to keep the reference voltage at twice the voltage at the common terminal.
摘要:
A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector UP signals (UP/DN) dependent on the sign of the phase difference; and a charge pump (61) comprising current generating means and controlled switches (64, 65) arranged to convert pulses on the detector signals to current pulses from a reference voltage (Vdd′) to a common terminal (Vloop) connected to the loop filter or to current pulses from the common terminal to ground. The current generating means comprises at least one resistor (62, 63) connected between the common terminal and the switches, and the charge pump comprises an operational amplifier (66) coupled to keep the reference voltage at twice the voltage at the common terminal.
摘要:
A wireless communication device includes at least two antennas with at least two corresponding receive chains. Selectively activating and deactivating the receivers as needed for a desired quality of reception controls the performance and power consumption of the wireless communication device. The wireless communication device may operate in a single receiver mode or a dual receiver diversity mode. In the dual receiver diversity mode, the wireless communication device may selectively control the gain of one or more antennas and/or reconfigure one or more receive chains to minimize power consumption while maintaining a desired performance.
摘要:
A method and apparatus for dynamically compensating for delay mismatch between a supply signal and an input signal of a power amplifier in polar modulation transmitters. One exemplary polar modulation transmitter according to the present invention comprises a power amplifier, a phase modulator, a regulator, a delay tracking circuit, and a delay circuit. The phase modulator derives the amplifier input signal responsive to one or more phase signals, while the regulator derives the amplifier supply signal responsive to an amplitude signal. Based on the amplitude signal and the amplifier supply signal, the delay tracking circuit tracks an observed amplitude path delay. The delay circuit adjusts a path delay associated with the phase signal, responsive to the observed amplitude path delay, to compensate for the delay mismatch.
摘要:
A frequency synthesizer circuit generates an output clock signal having a desired frequency relationship with an input reference signal, and offers essentially arbitrary relational values and adjustment resolution within any applicable circuit limits. The frequency synthesizer includes a ring oscillator circuit that provides multiple phases of its output clock signal, a phase selection circuit to select a phase of the output clock signal for feedback to an oscillator control circuit at each cycle of the reference signal according to a phase selection sequence. The oscillator control circuit generates a control signal responsive to comparing the selected phases of the output clock signal with the reference signal, and the phase selection circuit may include a modulator to generate phase selection sequences having desired time-average values that enable arbitrary frequency adjustability.
摘要:
A transimpedance stage amplifier converts a current input signal at an input node to a low impedance output voltage at an output node. The amplifier includes a resistor connected between the input node and the output node. A feedback loop is connected across the resistor, the feedback loop comprising a transistor, the transistor using the current input signal as a biasing current.
摘要:
In a communication transceiver receiving a signal from a signal source defined by a source impedance between first and second nodes, an amplifier is provided having an input impedance matched to the source impedance. The amplifier includes a first transconductance cell having a first transconductance related to the input impedance and including first and second transistors each having control, supply and output elements. The first transconductance cell receives the signal from the signal source at the first and second control elements and develops a modified version of the signal as an output current signal at the first and second output elements, respectively. The first and second transistors are interconnected such that the control element of the first transistor is connected to the output element of the second transistor, and the control element of the second transistor is connected to the output element of the first transistor. The amplifier further includes a second transconductance cell having a second transconductance related to the input impedance and including third and fourth transistors connected to the first and second output elements. The second transconductance cell combines currents appearing at the first and second output elements and develops a combined output current signal at respective output terminals thereof.
摘要:
Phase and gain of a transmit signal are measured at a transmitter by determining a first time delay having a first resolution at a measurement receiver between a reference signal from which the transmit signal is generated and a measured signal derived from the transmit signal by comparing amplitudes of the reference signal and the measured signal. A second time delay having a second resolution finer than the first resolution is determined at the measurement receiver between the reference signal and the measured signal based on the first time delay. The reference signal and the measured signal are time aligned at the measurement receiver based on the second time delay and the phase and gain of the transmit signal are estimated after the reference signal and the measured signal are time aligned.
摘要:
A frequency synthesizer according to the present invention digitally controls an analog oscillator to generate an analog output signal at a desired frequency. A digitizing circuit converts a feedback signal derived from the oscillator output signal to a digitized multi-phase feedback signal. A comparator compares the digitized multi-phase feedback signal to a reference signal generated by the reference signal generator to generate an error signal indicative of the phase error in the output signal. A control circuit generates a control signal based on the error signal to control the frequency of the oscillator output signal.
摘要:
Amplifier systems are provided with bias generators that substantially stabilize operating points of system parameters (e.g., drain current and transconductance) over PVT variations, substantially reduce body effects and Early effects, and substantially reduce system output noise. These advantages are realized without significantly increasing system size and/or power consumption.