公开(公告)号：US06708026B1

公开(公告)日：2004-03-16

申请号：US09481248

申请日：2000-01-11

申请人： Nikolaus Klemmer ,  Antonio J. Montalvo ,  Steven L. White

发明人： Nikolaus Klemmer ,  Antonio J. Montalvo ,  Steven L. White

IPC分类号： H04B126

CPC分类号： H03L7/1976 ,  H03D7/163

摘要： A programmable digital divider operates under the control of a division controller to derive a second synthesized frequency based on a first synthesized frequency. The programmable divider divides the first synthesized signal to derive the second synthesized signal. The division amount is an integer, but varies between integer values if necessary to achieve a non-integer average division value. The majority of the noise generated by the frequency synthesizer is generated away from the centerline frequency and is easily filtered by narrowband filter. The frequency synthesizer may optionally be incorporated into a modified phase-locked loop to generate the second synthesized signal. By using a digital divider, instead of a traditional phase-locked loop, these embodiments allow for integration of the frequency synthesizer onto an integrated circuit, thereby lowering cost and improving resistance to noise spurs. This approach is particularly suited to telecommunications applications.

摘要翻译： 可编程数字分频器在分频控制器的控制下操作，以基于第一合成频率导出第二合成频率。 可编程分频器分割第一合成信号以导出第二合成信号。 分割量是一个整数，但如果需要，可以在整数值之间变化，以获得非整数平均除法值。 由频率合成器产生的大部分噪声是从中心线频率产生的，并且容易被窄带滤波器滤波。 频率合成器可以可选地并入修改的锁相环以产生第二合成信号。 通过使用数字分频器而不是传统的锁相环，这些实施例允许将频率合成器集成到集成电路上，从而降低成本并提高对噪声的抵抗力。 这种方法特别适用于电信应用。

公开(公告)号：US06265947B1

公开(公告)日：2001-07-24

申请号：US09481461

申请日：2000-01-11

申请人： Nikolaus Klemmer ,  Steven L. White

发明人： Nikolaus Klemmer ,  Steven L. White

IPC分类号： H03L7095

CPC分类号： H03L7/14 ,  H03L7/0802 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/18 ,  H04W52/028 ,  Y02D70/122

摘要： A power conserving phase-locked loop achieves power savings by adding a switch which selectively enables the bias current for the charge pump associated with the phase comparator of the phase-locked loop. The switch is connected by a logic circuit to a counter that tracks the expected arrival time of a signal edge of the reference signal. Immediately prior to the arrival of the expected signal edge, the switch is enabled, thereby creating and applying the bias current to activate the charge pump in the event that a correction is needed to maintain the “lock” in the phase-locked loop. When the signal edge passes, the bias current is turned off again before the arrival of the next signal edge. This switching may result in a ten percent duty cycle in the biasing current, resulting in approximately a ninety percent power savings. The phase-locked loop may be used for a variety of applications, such as a frequency synthesizer in a receiver chain of wireless communications mobile terminals, where power consumption is a concern.

摘要翻译： 省电锁相环通过添加一个开关来实现功率节省，该开关选择性地启用与锁相环相位比较器相关联的电荷泵的偏置电流。 开关由逻辑电路连接到跟踪参考信号的信号边缘的预期到达时间的计数器。 在预期信号边缘到达之前，开关被使能，从而在需要进行校正以维持锁相环中的“锁定”的情况下，产生和施加偏置电流来激活电荷泵。 当信号边沿通过时，偏置电流在下一个信号边缘到达之前被再次关断。 这种切换可能导致偏置电流占用10％的周期，导致大约90％的功率节省。 锁相环可以用于各种应用，例如无线通信移动终端的接收机链中的频率合成器，其中功耗是关注的。

公开(公告)号：US06265902B1

公开(公告)日：2001-07-24

申请号：US09432897

申请日：1999-11-02

申请人： Nikolaus Klemmer ,  Steven L. White

发明人： Nikolaus Klemmer ,  Steven L. White

IPC分类号： H03D300

CPC分类号： H03L7/0891 ,  H03D13/004 ,  H03L7/183

摘要： An improved digital phase detector is provided for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge. The digital phase detector includes a detector circuit for detecting a cycle slip where two successive leading edges of one of the reference and frequency source signals are received before a leading edge of the other signal is received. An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to said detecting.

摘要翻译： 提供了一种改进的数字相位检测器，用于检测和补偿参考信号和频率源信号之间的循环滑移，每个参考和频率源信号包括脉冲，每个脉冲由前沿和后沿定义。 数字相位检测器包括检测器电路，用于检测在接收另一信号的前沿之前接收到参考和频率源信号之一的两个连续前沿的周期滑移。 输出电路可操作地耦合到检测器电路，用于响应于所述检测而形成校正信号。

公开(公告)号：US08638143B2

公开(公告)日：2014-01-28

申请号：US13511603

申请日：2010-11-16

申请人： Magnus Nilsson ,  Nikolaus Klemmer

发明人： Magnus Nilsson ,  Nikolaus Klemmer

IPC分类号： H03L7/06

CPC分类号： H03L7/1976 ,  H03L7/0891 ,  H03L7/0895

摘要： A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector signals (UP/DN) dependent on the sign of the phase difference; and a charge pump (61) comprising current generating means and controlled switches (64, 65) arranged to convert pulses on the detector signals to current pulses from a reference voltage (Vdd′) to a common terminal (Vloop) connected to the loop filter or to current pulses from the common terminal to ground. The current generating means comprises at least one resistor (62, 63) connected between the common terminal and the switches, and the charge pump comprises an operational amplifier (66) coupled to keep the reference voltage at twice the voltage at the common terminal.

摘要翻译： 锁相环频率合成器包括压控振荡器; 用于向振荡器提供控制电压的环路滤波器; 相位频率检测器，被配置为检测参考信号和从振荡器信号产生的反馈信号之间的相位差，并根据相位差的符号在检测器信号（UP / DN）上产生脉冲; 以及电荷泵（61），包括电流产生装置和受控开关（64,65），其被布置成将检测器信号上的脉冲转换成从参考电压（Vdd'）到连接到环路滤波器的公共端子（V loop）的电流脉冲 或从公共端到地的电流脉冲。 电流产生装置包括连接在公共端子和开关之间的至少一个电阻器（62,63），并且电荷泵包括耦合以将参考电压保持在公共端子处的电压的两倍的运算放大器（66）。

公开(公告)号：US20120274372A1

公开(公告)日：2012-11-01

申请号：US13511603

申请日：2010-11-16

申请人： Magnus Nilsson ,  Nikolaus Klemmer

发明人： Magnus Nilsson ,  Nikolaus Klemmer

IPC分类号： H03L7/06

CPC分类号： H03L7/1976 ,  H03L7/0891 ,  H03L7/0895

摘要： A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector UP signals (UP/DN) dependent on the sign of the phase difference; and a charge pump (61) comprising current generating means and controlled switches (64, 65) arranged to convert pulses on the detector signals to current pulses from a reference voltage (Vdd′) to a common terminal (Vloop) connected to the loop filter or to current pulses from the common terminal to ground. The current generating means comprises at least one resistor (62, 63) connected between the common terminal and the switches, and the charge pump comprises an operational amplifier (66) coupled to keep the reference voltage at twice the voltage at the common terminal.

摘要翻译： 锁相环频率合成器包括压控振荡器; 用于向振荡器提供控制电压的环路滤波器; 相位频率检测器，被配置为检测参考信号和从振荡器信号产生的反馈信号之间的相位差，并根据相位差的符号在检测器UP信号（UP / DN）上生成脉冲; 以及电荷泵（61），包括电流产生装置和受控开关（64,65），其被布置成将检测器信号上的脉冲转换成从参考电压（Vdd'）到连接到环路滤波器的公共端子（V loop）的电流脉冲 或从公共端到地的电流脉冲。 电流产生装置包括连接在公共端子和开关之间的至少一个电阻器（62,63），并且电荷泵包括耦合以将参考电压保持在公共端子处的电压的两倍的运算放大器（66）。

公开(公告)号：US07929985B2

公开(公告)日：2011-04-19

申请号：US10427872

申请日：2003-05-01

申请人： Ali Khayrallah ,  Tracy Fulghum ,  Nikolaus Klemmer

发明人： Ali Khayrallah ,  Tracy Fulghum ,  Nikolaus Klemmer

IPC分类号： H04M1/00

CPC分类号： H04B7/0871 ,  H04B7/0817 ,  H04B7/0842 ,  H04B7/0877 ,  H04B2201/709727 ,  Y02D70/1222 ,  Y02D70/1224 ,  Y02D70/1226 ,  Y02D70/1244 ,  Y02D70/444

摘要： A wireless communication device includes at least two antennas with at least two corresponding receive chains. Selectively activating and deactivating the receivers as needed for a desired quality of reception controls the performance and power consumption of the wireless communication device. The wireless communication device may operate in a single receiver mode or a dual receiver diversity mode. In the dual receiver diversity mode, the wireless communication device may selectively control the gain of one or more antennas and/or reconfigure one or more receive chains to minimize power consumption while maintaining a desired performance.

摘要翻译： 无线通信设备包括具有至少两个对应的接收链的至少两个天线。 根据所需的接收质量选择性地激活和去激活接收器来控制无线通信设备的性能和功耗。 无线通信设备可以在单个接收机模式或双重接收机分集模式下操作。 在双重接收机分集模式中，无线通信设备可以选择性地控制一个或多个天线的增益和/或重新配置一个或多个接收链，以最小化功耗，同时保持期望的性能。

公开(公告)号：US20060057976A1

公开(公告)日：2006-03-16

申请号：US10940880

申请日：2004-09-14

申请人： Nikolaus Klemmer

发明人： Nikolaus Klemmer

IPC分类号： H04B1/02

CPC分类号： H04L27/361 ,  H04L7/0041 ,  H04L7/0337

摘要： A method and apparatus for dynamically compensating for delay mismatch between a supply signal and an input signal of a power amplifier in polar modulation transmitters. One exemplary polar modulation transmitter according to the present invention comprises a power amplifier, a phase modulator, a regulator, a delay tracking circuit, and a delay circuit. The phase modulator derives the amplifier input signal responsive to one or more phase signals, while the regulator derives the amplifier supply signal responsive to an amplitude signal. Based on the amplitude signal and the amplifier supply signal, the delay tracking circuit tracks an observed amplitude path delay. The delay circuit adjusts a path delay associated with the phase signal, responsive to the observed amplitude path delay, to compensate for the delay mismatch.

摘要翻译： 一种用于动态地补偿极性调制发射机中的功率放大器的电源信号和输入信号之间的延迟失配的方法和装置。 根据本发明的一个示例性极性调制发射机包括功率放大器，相位调制器，调节器，延迟跟踪电路和延迟电路。 响应于一个或多个相位信号，相位调制器导出放大器输入信号，而稳压器响应幅度信号导出放大器电源信号。 基于振幅信号和放大器电源信号，延迟跟踪电路跟踪观察到的振幅路径延迟。 延迟电路响应于观察到的幅度路径延迟来调整与相位信号相关联的路径延迟，以补偿延迟失配。

公开(公告)号：US20050197073A1

公开(公告)日：2005-09-08

申请号：US10794830

申请日：2004-03-05

申请人： Nikolaus Klemmer

发明人： Nikolaus Klemmer

IPC分类号： H03L7/083 ,  H03L7/099 ,  H03L7/16 ,  H04B1/40

CPC分类号： H03L7/0996 ,  H03L7/083 ,  H03L7/16

摘要： A frequency synthesizer circuit generates an output clock signal having a desired frequency relationship with an input reference signal, and offers essentially arbitrary relational values and adjustment resolution within any applicable circuit limits. The frequency synthesizer includes a ring oscillator circuit that provides multiple phases of its output clock signal, a phase selection circuit to select a phase of the output clock signal for feedback to an oscillator control circuit at each cycle of the reference signal according to a phase selection sequence. The oscillator control circuit generates a control signal responsive to comparing the selected phases of the output clock signal with the reference signal, and the phase selection circuit may include a modulator to generate phase selection sequences having desired time-average values that enable arbitrary frequency adjustability.

摘要翻译： 频率合成器电路产生与输入参考信号具有期望频率关系的输出时钟信号，并且在任何适用的电路限制内提供基本上任意的关系值和调整分辨率。 频率合成器包括提供其输出时钟信号的多个相位的环形振荡器电路，相位选择电路，用于根据相位选择在参考信号的每个周期选择输出时钟信号的相位以反馈到振荡器控制电路 序列。 振荡器控制电路响应于将输出时钟信号的所选相位与参考信号进行比较而产生控制信号，并且相位选择电路可以包括调制器，以产生具有能够进行任意频率可调性的期望时间平均值的相位选择序列。

公开(公告)号：US06163235A

公开(公告)日：2000-12-19

申请号：US144945

申请日：1998-09-01

申请人： Nikolaus Klemmer

发明人： Nikolaus Klemmer

IPC分类号： H03D7/14 ,  H03F1/56 ,  H03F3/45 ,  H01P1/22

CPC分类号： H03F3/45085 ,  H03D7/1433 ,  H03D7/145 ,  H03D2200/0047 ,  H03D2200/0088 ,  H03F1/56

摘要： A transimpedance stage amplifier converts a current input signal at an input node to a low impedance output voltage at an output node. The amplifier includes a resistor connected between the input node and the output node. A feedback loop is connected across the resistor, the feedback loop comprising a transistor, the transistor using the current input signal as a biasing current.

摘要翻译： 跨阻级放大器将输入节点处的电流输入信号转换为输出节点处的低阻抗输出电压。 放大器包括连接在输入节点和输出节点之间的电阻器。 反馈回路连接在电阻两端，反馈回路包括晶体管，晶体管使用电流输入信号作为偏置电流。

公开(公告)号：US6150882A

公开(公告)日：2000-11-21

申请号：US215528

申请日：1998-12-18

申请人： Nikolaus Klemmer

发明人： Nikolaus Klemmer

IPC分类号： H03F3/45

CPC分类号： H03F3/45677 ,  H03F3/45179 ,  H03F3/45188 ,  H03F3/45713 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45172 ,  H03F2203/45228 ,  H03F2203/45318 ,  H03F2203/45394

摘要： In a communication transceiver receiving a signal from a signal source defined by a source impedance between first and second nodes, an amplifier is provided having an input impedance matched to the source impedance. The amplifier includes a first transconductance cell having a first transconductance related to the input impedance and including first and second transistors each having control, supply and output elements. The first transconductance cell receives the signal from the signal source at the first and second control elements and develops a modified version of the signal as an output current signal at the first and second output elements, respectively. The first and second transistors are interconnected such that the control element of the first transistor is connected to the output element of the second transistor, and the control element of the second transistor is connected to the output element of the first transistor. The amplifier further includes a second transconductance cell having a second transconductance related to the input impedance and including third and fourth transistors connected to the first and second output elements. The second transconductance cell combines currents appearing at the first and second output elements and develops a combined output current signal at respective output terminals thereof.

摘要翻译： 在通信收发信机中，从由第一和第二节点之间的源阻抗定义的信号源接收信号，提供具有与源阻抗匹配的输入阻抗的放大器。 放大器包括具有与输入阻抗相关的第一跨导的第一跨导单元，并且包括具有控制，电源和输出元件的第一和第二晶体管。 第一跨导单元在第一和第二控制元件处接收来自信号源的信号，并且分别在第一和第二输出元件处产生作为输出电流信号的信号的修改版本。 第一和第二晶体管被互连，使得第一晶体管的控制元件连接到第二晶体管的输出元件，第二晶体管的控制元件连接到第一晶体管的输出元件。 放大器还包括具有与输入阻抗相关的第二跨导的第二跨导单元，并且包括连接到第一和第二输出元件的第三和第四晶体管。 第二跨导单元组合出现在第一和第二输出元件处的电流，并在其各自的输出端产生组合的输出电流信号。