公开(公告)号：US20170338305A1

公开(公告)日：2017-11-23

申请号：US15160896

申请日：2016-05-20

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Paul D. Hurwitz ,  Edward Preisler ,  Marco Racanelli

IPC: H01L29/06 ,  H01L23/66 ,  H01L21/762

CPC classification number: H01L29/0688 ,  H01L21/76224 ,  H01L23/66 ,  H01L29/0638 ,  H01L29/0649

Abstract: A structure includes a field isolation region in a high resistivity substrate, a compensation implant region under the field isolation region in the high resistivity substrate, where the compensation implant region is configured to substantially eliminate a parasitic p-n junction under the field isolation region. The parasitic p-n junction is formed between trapped charges in the field isolation region and the high resistivity substrate. The compensation implant region includes a charge of a first conductivity type to compensate a parasitic charge of a second conductivity type under the field isolation region. The compensation implant region is configured to improve linearity of RF signals propagating through a metallization layer over the field isolation region. The structure further includes a deep trench extending through the field isolation region and the compensation implant region, and a damaged region adjacent the deep trench.

公开(公告)号：US20160379926A1

公开(公告)日：2016-12-29

申请号：US15190038

申请日：2016-06-22

Applicant: Newport Fab, LLC dba Jazz Semiconductor, Inc.

Inventor： David J. Howard ,  Hadi Jebory ,  Marco Racanelli

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/304 ,  H01L21/768 ,  H01L29/06 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/304 ,  H01L21/76841 ,  H01L21/76871 ,  H01L23/481 ,  H01L23/4827 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L29/0657

Abstract: A method of fabricating a semiconductor structure includes: grinding a backside surface of a semiconductor substrate such that the backside surface has a relatively high average roughness (Ra) (when compared with a backside surface subjected to chemical mechanical polishing (CMP)), and then, forming a backside metal structure on the backside surface while the backside surface has the relatively high average roughness. The backside surface can have an average roughness in the range of about 5 to 100 nanometers (or alternately, in the range of about 20 to 40 nanometers) when the backside metal structure is formed. The backside metal structure may be electrically coupled to through silicon vias (TSVs), which supply ground to semiconductor devices fabricated on a front side of the semiconductor substrate.

Abstract translation: 制造半导体结构的方法包括：研磨半导体衬底的背面，使得背面具有相对高的平均粗糙度（Ra）（与经过化学机械抛光（CMP）的背面相比），然后 在背面上形成背面金属结构，而背面具有较高的平均粗糙度。 当形成背面金属结构时，背面可以具有在约5至100纳米（或者替代地，在约20至40纳米的范围内）范围内的平均粗糙度。 背面金属结构可以电耦合到通过硅通孔（TSV），硅通孔（TSV）将制造在半导体衬底的前侧上的半导体器件提供接地。

公开(公告)号：US20130109176A1

公开(公告)日：2013-05-02

申请号：US13657007

申请日：2012-10-22

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Volker Blaschke ,  Todd Thibeault ,  Chris Cureton ,  Paul Hurwitz ,  Arjun Kar-Roy ,  David Howard ,  Marco Racanelli

IPC: H01L21/768

CPC classification number: H01L21/743 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.

公开(公告)号：US20210375618A1

公开(公告)日：2021-12-02

申请号：US17400712

申请日：2021-08-12

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Paul D. Hurwitz ,  Edward Preisler ,  David J. Howard ,  Marco Racanelli

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L23/66 ,  H03K17/687 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

公开(公告)号：US20210111249A1

公开(公告)日：2021-04-15

申请号：US16598803

申请日：2019-10-10

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Paul D. Hurwitz ,  Edward Preisler ,  David J. Howard ,  Marco Racanelli

IPC: H01L29/10 ,  H01L23/66 ,  H01L21/02 ,  H01L21/324 ,  H01L27/088

Abstract: A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices.

公开(公告)号：US20180323114A1

公开(公告)日：2018-11-08

申请号：US15587969

申请日：2017-05-05

Applicant: Newport Fab, LLC dba Jazz Semiconductor, Inc.

Inventor： Edward J. Preisler ,  Marco Racanelli ,  Paul D. Hurwitz

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  H01L21/266 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0646

Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.

公开(公告)号：US20190109055A1

公开(公告)日：2019-04-11

申请号：US16026006

申请日：2018-07-02

Applicant: Newport Fab, LLC dba Jazz Semiconductor, Inc.

Inventor： Edward J. Preisler ,  Paul D. Hurwitz ,  Marco Racanelli ,  David J. Howard

IPC: H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/737 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/165

Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

公开(公告)号：US20210111019A1

公开(公告)日：2021-04-15

申请号：US16597779

申请日：2019-10-09

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Paul D. Hurwitz ,  Edward Preisler ,  David J. Howard ,  Marco Racanelli

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L21/762 ,  H01L23/66 ,  H03K17/687

Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

公开(公告)号：US20190109054A1

公开(公告)日：2019-04-11

申请号：US15727159

申请日：2017-10-06

Applicant: Newport Fab, LLC dba Jazz Semiconductor, Inc.

Inventor： Edward J. Preisler ,  Paul D. Hurwitz ,  Marco Racanelli ,  David J. Howard

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737 ,  H01L27/12 ,  H01L29/165

Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

公开(公告)号：US20180323115A1

公开(公告)日：2018-11-08

申请号：US15941234

申请日：2018-03-30

Applicant: Newport Fab, LLC dba Jazz Semiconductor, Inc.

Inventor： Edward J. Preisler ,  Marco Racanelli ,  Paul D. Hurwitz

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/266 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0646

Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.