公开(公告)号：US09887123B2

公开(公告)日：2018-02-06

申请号：US14886347

申请日：2015-10-19

Applicant: Newport Fab, LLC

Inventor： Arjun Kar-Roy ,  David J. Howard

IPC: H01L21/74 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/74 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

公开(公告)号：US09105681B2

公开(公告)日：2015-08-11

申请号：US13657007

申请日：2012-10-22

Applicant: Newport Fab, LLC

Inventor： Volker Blaschke ,  Todd Thibeault ,  Chris Cureton ,  Paul Hurwitz ,  Arjun Kar-Roy ,  David Howard ,  Marco Racanelli

IPC: H01L21/768 ,  H01L21/74

CPC classification number: H01L21/743 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.

Abstract translation: 根据示例性实施例，提供了包括至少一个深硅通孔的半导体管芯。 深硅通孔包括深硅通孔开口，其延伸穿过半导体管芯的至少一个预金属介电层，半导体管芯的至少一个外延层，并且部分地延伸到半导体管芯的导电衬底中。 深硅通孔还包括通过开口位于深硅中的导电塞，并与导电基底形成电接触。 深硅通孔可以包括侧壁电介质层和底部导电层。 还公开了制造深硅通孔的方法。 深硅通孔用于例如为半导体管芯中的功率晶体管提供接地连接。

公开(公告)号：US20180247856A1

公开(公告)日：2018-08-30

申请号：US15967449

申请日：2018-04-30

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Arjun Kar-Roy ,  David J. Howard

IPC: H01L21/74 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/74 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

公开(公告)号：US20160118339A1

公开(公告)日：2016-04-28

申请号：US14886347

申请日：2015-10-19

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Arjun Kar-Roy ,  David J. Howard

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/74 ,  H01L23/532

CPC classification number: H01L21/74 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

Abstract translation: 公开了具有隔离的深衬底通孔的结构，其具有减小的间距和增加的纵横比。 该结构包括在掩埋氧化物层上的器件层，延伸穿过器件层的深沟槽，深沟槽中的介电填料，介电填料中的通孔，以及通孔中的导电填料，其是隔离的深衬底通孔。 介电填料可以包括氧化硅。 导电填料可以包括钨或铜。 在深沟槽内的隔离的深衬底通孔中的相邻对具有等于或小于1.0微米的间距。

公开(公告)号：US20130109176A1

公开(公告)日：2013-05-02

申请号：US13657007

申请日：2012-10-22

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Volker Blaschke ,  Todd Thibeault ,  Chris Cureton ,  Paul Hurwitz ,  Arjun Kar-Roy ,  David Howard ,  Marco Racanelli

IPC: H01L21/768

CPC classification number: H01L21/743 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.

公开(公告)号：US20150368094A1

公开(公告)日：2015-12-24

申请号：US14719187

申请日：2015-05-21

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： David J. Howard ,  Michael J. DeBar ,  Jeff Rose ,  Arjun Kar-Roy

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00095 ,  B81B3/007 ,  B81B7/0006 ,  B81B2201/0207 ,  B81B2203/0361 ,  B81C1/00111 ,  B81C1/00166 ,  B81C1/00658 ,  H01L21/47635 ,  H01L21/76883 ,  H01L29/0676 ,  H01L29/417

Abstract: Self-supported MEMS structure and method for its formation are disclosed. An exemplary method includes forming a polymer layer over a MEMS plate over a substrate, forming a via collar along sidewalls of a first portion of a trench over the polymer layer, and forming a second portion of the trench within the polymer layer. The method also includes forming an oxide liner in the trench lining sidewalls of the via collar and sidewalls of the second portion of the trench, depositing a metallic filler in the trench to form a via, and forming a metal cap layer over the via collar and the metallic filler. The method further includes removing a portion of the metal cap layer to form a via cap, and removing the polymer layer such that the via is supported only on a bottom thereof by the substrate. An exemplary structure formed by the disclosed method is also disclosed.

Abstract translation: 公开了自支撑MEMS结构及其形成方法。 一种示例性方法包括在衬底上方的MEMS板上形成聚合物层，在聚合物层上形成沿沟槽第一部分的侧壁的通孔环，以及在聚合物层内形成沟槽的第二部分。 该方法还包括在通孔环的沟槽衬里和沟槽的第二部分的侧壁的沟槽衬里中形成氧化物衬垫，在沟槽中沉积金属填料以形成通孔，并在通孔环上形成金属盖层， 金属填料。 该方法还包括去除金属盖层的一部分以形成通孔盖，以及去除聚合物层，使得通孔仅由基底在其底部支撑。 还公开了通过公开的方法形成的示例性结构。

公开(公告)号：US09377350B2

公开(公告)日：2016-06-28

申请号：US14827112

申请日：2015-08-14

Applicant: Newport Fab, LLC

Inventor： David J. Howard ,  Jeff Rose ,  Arjun Kar-Roy ,  Michael J. DeBar

IPC: G01J1/04

CPC classification number: G01J1/0414 ,  G01J5/0225 ,  G01J5/024 ,  G01J5/20

Abstract: A light sensor having a chemically resistant and robust reflector stack is disclosed. The reflector stack is formed over a substrate, and includes an adhesion layer, a patterned reflector layer over the adhesion layer, and a smoothing layer over the patterned reflector layer. The patterned reflector layer has a substantially flat top surface. A conformal passivation layer covers the reflector stack. An absorbing layer is situated above the reflector stack and separated from the reflector stack. The absorbing layer is supported by vias over the substrate. The absorbing layer is connected to at least one resistor, where a resistance of the at least one resistor varies in response to light absorbed by the absorbing layer. The vias are disposed on via landing pads on the substrate.

Abstract translation: 公开了一种具有耐化学腐蚀和坚固的反射器叠层的光传感器。 反射器堆叠形成在衬底上，并且包括粘合层，在粘合层上的图案化反射层，以及在图案化反射器层上方的平滑层。 图案化的反射层具有基本平坦的顶表面。 保形钝化层覆盖反射层。 吸收层位于反射器叠层上方并与反射器叠层分离。 吸收层由衬底上的通孔支撑。 吸收层连接到至少一个电阻器，其中至少一个电阻器的电阻响应于吸收层吸收的光而变化。 通孔设置在基板上的通路板上。

公开(公告)号：US20170330789A1

公开(公告)日：2017-11-16

申请号：US15664157

申请日：2017-07-31

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Arjun Kar-Roy ,  David J. Howard

IPC: H01L21/74 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/74 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

公开(公告)号：US09458011B2

公开(公告)日：2016-10-04

申请号：US14719087

申请日：2015-05-21

Applicant: Newport Fab, LLC

Inventor： David J. Howard ,  Michael J. DeBar ,  Jeff Rose ,  Arjun Kar-Roy

IPC: H01L21/4763 ,  B81C1/00 ,  B81B3/00 ,  H01L29/417 ,  H01L21/768

CPC classification number: B81C1/00111 ,  B81B3/007 ,  B81B2203/0307 ,  B81C1/00166 ,  B81C1/00658 ,  H01L21/47635 ,  H01L21/76883 ,  H01L29/417

Abstract: Self-supported MEMS structure and method for its formation are disclosed. An exemplary method includes forming a polymer layer over a MEMS plate over a substrate, forming a trench over the MEMS plate, forming an oxide liner in the trench on sidewalls of the trench, forming a metal liner over the oxide liner in the trench, and depositing a metallic filler in the trench to form a via. The method further includes removing the polymer layer such that the via and the MEMS plate form the self-supported MEMS structure, where the oxide liner provides mechanical rigidity for the metallic filler of the via. An exemplary structure formed by the disclosed method is also disclosed.

Abstract translation: 公开了自支撑MEMS结构及其形成方法。 示例性方法包括在衬底上方的MEMS板上形成聚合物层，在MEMS板上形成沟槽，在沟槽的侧壁上形成沟槽中的氧化物衬垫，在沟槽中的氧化物衬垫上形成金属衬垫，以及 在沟槽中沉积金属填料以形成通孔。 该方法还包括去除聚合物层，使得通孔和MEMS板形成自支撑的MEMS结构，其中氧化物衬垫为通孔的金属填料提供机械刚性。 还公开了通过公开的方法形成的示例性结构。

公开(公告)号：US20160069739A1

公开(公告)日：2016-03-10

申请号：US14827112

申请日：2015-08-14

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： David J. Howard ,  Jeff Rose ,  Arjun Kar-Roy ,  Michael J. DeBar

IPC: G01J1/04

CPC classification number: G01J1/0414 ,  G01J5/0225 ,  G01J5/024 ,  G01J5/20

Abstract: A light sensor having a chemically resistant and robust reflector stack is disclosed. The reflector stack is formed over a substrate, and includes an adhesion layer, a patterned reflector layer over the adhesion layer, and a smoothing layer over the patterned reflector layer. The patterned reflector layer has a substantially flat top surface. A conformal passivation layer covers the reflector stack. An absorbing layer is situated above the reflector stack and separated from the reflector stack. The absorbing layer is supported by vias over the substrate. The absorbing layer is connected to at least one resistor, where a resistance of the at least one resistor varies in response to light absorbed by the absorbing layer. The vias are disposed on via landing pads on the substrate.

Abstract translation: 公开了一种具有耐化学腐蚀和坚固的反射器叠层的光传感器。 反射器堆叠形成在衬底上，并且包括粘合层，在粘合层上的图案化反射层，以及在图案化反射器层上方的平滑层。 图案化的反射层具有基本平坦的顶表面。 保形钝化层覆盖反射层。 吸收层位于反射器叠层上方并与反射器叠层分离。 吸收层由衬底上的通孔支撑。 吸收层连接到至少一个电阻器，其中至少一个电阻器的电阻响应于吸收层吸收的光而变化。 通孔设置在基板上的通路板上。