公开(公告)号：US11378600B2

公开(公告)日：2022-07-05

申请号：US16933643

申请日：2020-07-20

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Ranjeet Kumar Gupta ,  Xu Zhang

IPC: G01R19/165 ,  G06F13/42 ,  H04B1/16 ,  H03H7/00

Abstract: A circuit is disclosed. The circuit includes an input port, an output port, a squelch detector and a disconnect detector. The squelch detector and the disconnect detector are enabled or disabled by a signal such that only one of the squelch detector and the disconnect detector is active at a given time. When the squelch detector is active, a threshold generator generates a squelch threshold for the squelch detector based on a squelch configuration data indicative of a predefined squelch threshold. When the disconnect detector is active, the threshold generator generates a disconnect threshold for the disconnect detector based on a disconnect configuration data indicative of a predefined disconnect threshold.

公开(公告)号：US20220018881A1

公开(公告)日：2022-01-20

申请号：US16933643

申请日：2020-07-20

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Ranjeet Kumar Gupta ,  Xu Zhang

IPC: G01R19/165 ,  H04B1/16 ,  G06F13/42

Abstract: A circuit is disclosed. The circuit includes an input port, an output port, a squelch detector and a disconnect detector. The squelch detector and the disconnect detector are enabled or disabled by a signal such that only one of the squelch detector and the disconnect detector is active at a given time. When the squelch detector is active, a threshold generator generates a squelch threshold for the squelch detector based on a squelch configuration data indicative of a predefined squelch threshold. When the disconnect detector is active, the threshold generator generates a disconnect threshold for the disconnect detector based on a disconnect configuration data indicative of a predefined disconnect threshold.

公开(公告)号：US10976351B2

公开(公告)日：2021-04-13

申请号：US16273230

申请日：2019-02-12

Applicant: NXP B.V.

Inventor： Xu Zhang ,  Siamak Delshadpour ,  Ahmad Yazdi

IPC: G01R15/14 ,  G01R19/165 ,  G01R19/25 ,  G01R27/08 ,  G01R27/16

Abstract: One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.

公开(公告)号：US10812067B1

公开(公告)日：2020-10-20

申请号：US16435413

申请日：2019-06-07

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Xu Zhang

IPC: H03K17/687 ,  H03H11/02 ,  H03K17/60

Abstract: Embodiments of redrivers and resistive units for redrivers are disclosed. In an embodiment, a resistive unit for a redriver includes at least one resistor connected to an input/output terminal of the redriver, at least one switch serially connected to the at least one resistor, and a voltage regulator connected to the at least one switch and configured to generate a termination voltage for the at least one switch. Instead of grounding the at least one resistor, using the voltage regulator can avoid large voltage jump at input/output terminals to keep connected devices safe.

公开(公告)号：US20210359884A1

公开(公告)日：2021-11-18

申请号：US16876970

申请日：2020-05-18

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Xu Zhang ,  Tong Liu ,  Samuel Michael Palermo

IPC: H04L25/03

Abstract: A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

公开(公告)号：US20200256894A1

公开(公告)日：2020-08-13

申请号：US16273230

申请日：2019-02-12

Applicant: NXP B.V.

Inventor： Xu Zhang ,  Siamak Delshadpour ,  Ahmad Yazdi

IPC: G01R15/14 ,  G01R19/25 ,  G01R19/165 ,  G01R27/16 ,  G01R27/08

Abstract: One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.

公开(公告)号：US10742215B1

公开(公告)日：2020-08-11

申请号：US16417407

申请日：2019-05-20

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Xu Zhang

IPC: H03K19/0185

Abstract: A circuit for translating a voltage of a digital signal from a first voltage level of a first voltage domain to a second voltage level of a second voltage domain is disclosed. The circuit includes a configurable circuit to be coupled between the first voltage domain and the second voltage domain. The configurable circuit includes a plurality of parallel data paths, wherein the configurable circuit is configured to enable only one of the plurality of data paths at a given time. A first path in the plurality of parallel data paths is configured to be enabled when the first voltage level is greater than the second voltage level and a second path in the plurality of parallel data paths is configured to be enabled when the first voltage level is lesser than the second voltage level.

公开(公告)号：US10560080B1

公开(公告)日：2020-02-11

申请号：US16183698

申请日：2018-11-07

Applicant: NXP B.V.

Inventor： Xu Zhang ,  Siamak Delshadpour ,  Ahmad Yazdi

IPC: H03K5/156

Abstract: A duty cycle correction circuit is disclosed. The duty cycle correction circuit includes an input stage, an output stage and a feedback component including a feedback amplifier and a low pass filter. The feedback component compares and adjusts the duty cycle of a signal from an input stage to a target value via a control voltage. The input stage reduces the rise and fall times of received signal to increase the duty cycle sensitivity to a control voltage from the feedback component. The output of the output stage is coupled to the input of the feedback component and the output stage amplifiers the duty cycle adjusted signal processed by both input stage and feedback component.

公开(公告)号：US10530377B1

公开(公告)日：2020-01-07

申请号：US16157996

申请日：2018-10-11

Applicant: NXP B.V.

Inventor： Xu Zhang

IPC: H03M1/06

Abstract: A current digital to analog converter (DAC) including an offset array including a plurality of unit cells of a first size, and a trimming array including a plurality of unit cells having the first size and a plurality of half cells, wherein the half cells have a larger size than the plurality of unit cells.

公开(公告)号：US09621148B2

公开(公告)日：2017-04-11

申请号：US14263814

申请日：2014-04-28

Applicant: NXP B.V.

Inventor： Jong Kim ,  Xu Zhang

IPC: H03K17/687 ,  H03K17/0412

CPC classification number: H03K17/04123

Abstract: Switching circuits are implemented in a manner that facilitates fast switching, which can be effected while also maintaining relatively low power dissipation. As may be implemented in connection with one or more embodiments, an apparatus includes a transistor connected between an input port and an output port, and a gate that switches between on and off states. A charge storage circuit stores a charge, and a switching circuit operates by switching the transistor between the on and off states as follows. In a first charging mode, a voltage is coupled across the charge storage circuit and a charge is stored therein, while decoupling the transistor from the charge storage circuit. In a second discharge mode, the transistor is switched from the off state to the on state, while coupling the stored charge across the gate and one of the source and drain of the transistor.