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公开(公告)号:US20210359884A1
公开(公告)日:2021-11-18
申请号:US16876970
申请日:2020-05-18
Applicant: NXP B.V.
Inventor: Siamak Delshadpour , Xu Zhang , Tong Liu , Samuel Michael Palermo
IPC: H04L25/03
Abstract: A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.
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公开(公告)号:US11228470B2
公开(公告)日:2022-01-18
申请号:US16876970
申请日:2020-05-18
Applicant: NXP B.V.
Inventor: Siamak Delshadpour , Xu Zhang , Tong Liu , Samuel Michael Palermo
IPC: H04L25/03
Abstract: A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.
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公开(公告)号:US11206160B2
公开(公告)日:2021-12-21
申请号:US16876854
申请日:2020-05-18
Applicant: NXP B.V.
Inventor: Siamak Delshadpour , Tong Liu , Samuel Michael Palermo
IPC: H04L25/03
Abstract: A high bandwidth continuous time linear equalization (HBCTLE) circuit is disclosed. The HBCTLE circuit includes a continuous time linear equalization (CTLE) circuit and a gain circuit coupled with an output of the CTLE circuit. A feedback circuit is coupled between the output of the CTLE circuit and an output of the gain circuit.
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公开(公告)号:US20210359883A1
公开(公告)日:2021-11-18
申请号:US16876854
申请日:2020-05-18
Applicant: NXP B.V.
Inventor: Siamak Delshadpour , Tong Liu , Samuel Michael Palermo
IPC: H04L25/03
Abstract: A high bandwidth continuous time linear equalization (HBCTLE) circuit is disclosed. The HBCTLE circuit includes a continuous time linear equalization (CTLE) circuit and a gain circuit coupled with an output of the CTLE circuit. A feedback circuit is coupled between the output of the CTLE circuit and an output of the gain circuit.
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