公开(公告)号：US20150169817A1

公开(公告)日：2015-06-18

申请号：US14250168

申请日：2014-04-10

Applicant: NXP B.V.

Inventor： Jong Kim ,  James Spehar ,  Xu Zhang

IPC: G06F17/50 ,  H01L23/495

CPC classification number: G06F17/5072 ,  G06F17/5036 ,  G06F17/5077 ,  G06F2217/40 ,  H01L23/64 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various example embodiments are directed to methods and apparatuses for implementing a circuit design within an integrated circuit (IC) package. A respective capacitance is determined for each die contact of a circuit design. A respective target inductance range is selected for each of the plurality of die contacts based on the determined capacitance. A segmentation of the circuit design is determined as a function of the target inductance ranges. The segmentation defines an implementation of the circuit design on a plurality of IC dies. The IC dies are placed at respective locations on the substrate, based on the resulting inductances of connections (e.g., conductive traces) between the die contacts and terminals of the IC package.

Abstract translation: 各种示例性实施例涉及用于实现集成电路（IC）封装内的电路设计的方法和装置。 对于电路设计的每个管芯接触确定相应的电容。 基于所确定的电容，为多个管芯触点中的每一个选择相应的目标电感范围。 电路设计的分割被确定为目标电感范围的函数。 分割定义了多个IC管芯上的​​电路设计的实现。 基于所得到的管芯触点和IC封装端子之间的连接（例如，导电迹线）的电感，将IC管芯放置在基板上的相应位置处。

公开(公告)号：US09385703B2

公开(公告)日：2016-07-05

申请号：US14256799

申请日：2014-04-18

Applicant: NXP B.V.

Inventor： Jong Kim ,  Xu Zhang

IPC: H01P1/22 ,  H03K17/687 ,  G11C7/00 ,  G11C16/26 ,  H03K17/14 ,  H03K17/30 ,  H03H11/24 ,  G11C5/14 ,  H03K17/00

CPC classification number: H03K17/145 ,  G11C5/146 ,  H03H11/245 ,  H03K17/005 ,  H03K17/302 ,  H03K17/687 ,  H03K2217/0018 ,  H03K2217/0054

Abstract: Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate. A body bias circuit is configured to bias the body of the transistor based on a voltage of the data signal to reduce variation in the on-resistance exhibited by the first transistor. As a result of the reduced variation in the on resistance, attenuation of the data signal is reduced.

Abstract translation: 各种示例性实施例涉及用于减轻由于身体效应引起的晶体管中的导通电阻变化和信号衰减的方法和电路。 在一些实施例中，一种装置包括晶体管，其配置为响应于提供给栅极的控制信号，从源极或漏极中的第一源极或漏极的另一个提供数据信号。 体偏置电路被配置为基于数据信号的电压来偏置晶体管的主体，以减小由第一晶体管显示的导通电阻的变化。 由于导通电阻的变化减小，数据信号的衰减减小。

公开(公告)号：US09621148B2

公开(公告)日：2017-04-11

申请号：US14263814

申请日：2014-04-28

Applicant: NXP B.V.

Inventor： Jong Kim ,  Xu Zhang

IPC: H03K17/687 ,  H03K17/0412

CPC classification number: H03K17/04123

Abstract: Switching circuits are implemented in a manner that facilitates fast switching, which can be effected while also maintaining relatively low power dissipation. As may be implemented in connection with one or more embodiments, an apparatus includes a transistor connected between an input port and an output port, and a gate that switches between on and off states. A charge storage circuit stores a charge, and a switching circuit operates by switching the transistor between the on and off states as follows. In a first charging mode, a voltage is coupled across the charge storage circuit and a charge is stored therein, while decoupling the transistor from the charge storage circuit. In a second discharge mode, the transistor is switched from the off state to the on state, while coupling the stored charge across the gate and one of the source and drain of the transistor.

公开(公告)号：US09430604B2

公开(公告)日：2016-08-30

申请号：US14250168

申请日：2014-04-10

Applicant: NXP B.V.

Inventor： Jong Kim ,  James Spehar ,  Xu Zhang

IPC: G06F17/50 ,  H01L23/64 ,  H01L25/065

CPC classification number: G06F17/5072 ,  G06F17/5036 ,  G06F17/5077 ,  G06F2217/40 ,  H01L23/64 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various example embodiments are directed to methods and apparatuses for implementing a circuit design within an integrated circuit (IC) package. A respective capacitance is determined for each die contact of a circuit design. A respective target inductance range is selected for each of the plurality of die contacts based on the determined capacitance. A segmentation of the circuit design is determined as a function of the target inductance ranges. The segmentation defines an implementation of the circuit design on a plurality of IC dies. The IC dies are placed at respective locations on the substrate, based on the resulting inductances of connections (e.g., conductive traces) between the die contacts and terminals of the IC package.

Abstract translation: 各种示例性实施例涉及用于实现集成电路（IC）封装内的电路设计的方法和装置。 对于电路设计的每个管芯接触确定相应的电容。 基于所确定的电容，为多个管芯触点中的每一个选择相应的目标电感范围。 电路设计的分割被确定为目标电感范围的函数。 分割定义了多个IC管芯上的​​电路设计的实现。 基于所得到的管芯触点和IC封装端子之间的连接（例如，导电迹线）的电感，将IC管芯放置在基板上的相应位置处。

公开(公告)号：US20150180464A1

公开(公告)日：2015-06-25

申请号：US14256799

申请日：2014-04-18

Applicant: NXP B.V.

Inventor： Jong Kim ,  Xu Zhang

IPC: H03K17/14

CPC classification number: H03K17/145 ,  G11C5/146 ,  H03H11/245 ,  H03K17/005 ,  H03K17/302 ,  H03K17/687 ,  H03K2217/0018 ,  H03K2217/0054

Abstract: Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate. A body bias circuit is configured to bias the body of the transistor based on a voltage of the data signal to reduce variation in the on-resistance exhibited by the first transistor. As a result of the reduced variation in the on resistance, attenuation of the data signal is reduced.

Abstract translation: 各种示例性实施例涉及用于减轻由于身体效应引起的晶体管中的导通电阻变化和信号衰减的方法和电路。 在一些实施例中，一种装置包括晶体管，其配置为响应于提供给栅极的控制信号，从源极或漏极中的第一源极或漏极的另一个提供数据信号。 体偏置电路被配置为基于数据信号的电压来偏置晶体管的主体，以减小由第一晶体管显示的导通电阻的变化。 由于导通电阻的变化减小，数据信号的衰减减小。

公开(公告)号：US20150180460A1

公开(公告)日：2015-06-25

申请号：US14263814

申请日：2014-04-28

Applicant: NXP B.V.

Inventor： Jong Kim ,  Xu Zhang

IPC: H03K17/0412 ,  H03K3/012

CPC classification number: H03K17/04123

Abstract: Switching circuits are implemented in a manner that facilitates fast switching, which can be effected while also maintaining relatively low power dissipation. As may be implemented in connection with one or more embodiments, an apparatus includes a transistor connected between an input port and an output port, and a gate that switches between on and off states. A charge storage circuit stores a charge, and a switching circuit operates by switching the transistor between the on and off states as follows. In a first charging mode, a voltage is coupled across the charge storage circuit and a charge is stored therein, while decoupling the transistor from the charge storage circuit. In a second discharge mode, the transistor is switched from the off state to the on state, while coupling the stored charge across the gate and one of the source and drain of the transistor.

Abstract translation: 切换电路以促进快速切换的方式实现，其可以在保持相对低的功率消耗的同时进行。 如可以结合一个或多个实施例来实现的，装置包括连接在输入端口和输出端口之间的晶体管，以及在导通和截止状态之间切换的栅极。 电荷存储电路存储电荷，并且开关电路通过如下所述在导通和截止状态之间切换晶体管而工作。 在第一充电模式中，电荷跨过电荷存储电路耦合，并且在其中存储电荷，同时使晶体管与电荷存储电路分离。 在第二放电模式中，晶体管从截止状态切换到导通状态，同时将存储的电荷跨过晶体管的栅极和源极和漏极之一耦合。