公开(公告)号：US10417158B1

公开(公告)日：2019-09-17

申请号：US16183729

申请日：2018-11-07

Applicant: NXP B.V.

Inventor： Anu Mathew ,  Abhijeet Chandrakant Kulkarni ,  Siamak Delshadpour

IPC: G06F13/40 ,  G06F13/42 ,  H02J7/00

Abstract: A circuit for detecting charger connection through a universal serial bus (UBS) connector is disclosed. The circuit includes a comparator having a first input coupled to a fixed voltage reference and a second input coupled to D+ pin of the USB connector, a voltage controlled current source (VCCS) coupled having a first terminal coupled to a supply and a second terminal coupled to the D+ pin and a resistor coupled between the first terminal and the second terminal of the VCCS. The VCCS is configured to bring voltage at the D+ pin within a preselected voltage range at the D+ pin when the voltage at the D+ pin varies beyond the preselected voltage range.

公开(公告)号：US11457524B2

公开(公告)日：2022-09-27

申请号：US16397709

申请日：2019-04-29

Applicant: NXP B.V.

Inventor： Mahmoud Mohamed Amin El Sabbagh ,  Anu Mathew ,  Siamak Delshadpour

IPC: H05K1/02

Abstract: A chip includes a plurality of ground conductors that at least partially surround a signal conductor on a same die. The signal conductor carries an interface (e.g., high speed) signal, and the ground conductors filter electromagnetic interference generated by the signal carried by the signal conductor. A chip package includes a plurality of ground pins around a signal pin that carries an interface signal. The ground pins filter electromagnetic interference generated by the signal carried by the signal pin. A printed circuit board includes a plurality of ground conductors around a signal line. The ground conductors are in vias and filter electromagnetic interference generated by an interface signal carried by the signal line.

公开(公告)号：US10938203B2

公开(公告)日：2021-03-02

申请号：US16173898

申请日：2018-10-29

Applicant: NXP B.V.

Inventor： Anu Mathew ,  Guido Wouter Willem Quax

IPC: H02H9/04

Abstract: One example discloses a voltage limiting device, including: a first I/O port; a second I/O port; a voltage limiter, coupled to the first and second I/O ports, and configured to shunt a voltage received on the first and/or second I/O ports having an absolute value greater than a voltage limit; wherein the voltage limiter includes a first portion and a second portion; wherein the first portion includes a first current shunt coupled between the first I/O port and a mid-net, and a second current shunt coupled between the second I/O port and the mid-net; and wherein the second portion includes a third current shunt having one end coupled to the mid-net and another end coupled to a ground.