Invention Grant
- Patent Title: Integrated filter for de-sense reduction
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Application No.: US16397709Application Date: 2019-04-29
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Publication No.: US11457524B2Publication Date: 2022-09-27
- Inventor: Mahmoud Mohamed Amin El Sabbagh , Anu Mathew , Siamak Delshadpour
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H05K1/02
- IPC: H05K1/02

Abstract:
A chip includes a plurality of ground conductors that at least partially surround a signal conductor on a same die. The signal conductor carries an interface (e.g., high speed) signal, and the ground conductors filter electromagnetic interference generated by the signal carried by the signal conductor. A chip package includes a plurality of ground pins around a signal pin that carries an interface signal. The ground pins filter electromagnetic interference generated by the signal carried by the signal pin. A printed circuit board includes a plurality of ground conductors around a signal line. The ground conductors are in vias and filter electromagnetic interference generated by an interface signal carried by the signal line.
Public/Granted literature
- US20200344872A1 INTEGRATED FILTER FOR DE-SENSE REDUCTION Public/Granted day:2020-10-29
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