公开(公告)号：US07106653B2

公开(公告)日：2006-09-12

申请号：US10993577

申请日：2004-11-19

申请人： Myeong-O Kim ,  Sung-Min Seo

发明人： Myeong-O Kim ,  Sung-Min Seo

IPC分类号： G11C8/00

CPC分类号： G11C7/04 ,  G11C7/1042 ,  G11C7/1066 ,  G11C2207/2281

摘要： The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

摘要翻译： 本发明公开了一种包括第一和第二存储体的半导体存储器件。 第一控制信号产生电路响应外部时钟产生第一控制信号。 第一数据输出电路响应于第一控制信号发送第一输出数据。 内部时钟信号发生电路响应于外部时钟输出第一和第二缓冲时钟信号。 第二控制信号发生电路响应于第一缓冲时钟信号和第一控制信号产生第二控制信号。 第二数据输出电路响应于第二控制信号发送第二输出数据。 第三数据输出电路响应于第一和第二缓冲时钟信号发送第三输出数据。 本发明防止由电源电压和温度变化引起的数据读取错误。

公开(公告)号：US20050122830A1

公开(公告)日：2005-06-09

申请号：US10993577

申请日：2004-11-19

申请人： Myeong-O Kim ,  Sung-Min Seo

发明人： Myeong-O Kim ,  Sung-Min Seo

IPC分类号： G11C11/40 ,  G11C7/10 ,  G11C8/00

CPC分类号： G11C7/04 ,  G11C7/1042 ,  G11C7/1066 ,  G11C2207/2281

摘要： The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

摘要翻译： 本发明公开了一种包括第一和第二存储体的半导体存储器件。 第一控制信号产生电路响应外部时钟产生第一控制信号。 第一数据输出电路响应于第一控制信号发送第一输出数据。 内部时钟信号发生电路响应于外部时钟输出第一和第二缓冲时钟信号。 第二控制信号发生电路响应于第一缓冲时钟信号和第一控制信号产生第二控制信号。 第二数据输出电路响应于第二控制信号发送第二输出数据。 第三数据输出电路响应于第一和第二缓冲时钟信号发送第三输出数据。 本发明防止由电源电压和温度变化引起的数据读取错误。

公开(公告)号：US07643364B2

公开(公告)日：2010-01-05

申请号：US12004291

申请日：2007-12-20

申请人： Jong-Cheol Lee ,  Myeong-O Kim

发明人： Jong-Cheol Lee ,  Myeong-O Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

摘要： A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed. The semiconductor memory device includes a sense amplification enable signal control portion which receives an initial sense amplification enable signal, sequentially delays the initial sense amplification enable signal by a plurality of predetermined time periods and selectively outputs a plurality of delayed sense amplification enable signals in view of both an operation speed and a manufacturing yield of a semiconductor memory device; a plurality of clocked sense amplifiers which each receive an output signal of the I/O sense amplifier, amplify the output signal of the I/O sense amplifier in response to each of the plurality of delayed sense amplification enable signals, and sequentially output an output signal of a power voltage level or a ground voltage level in response; and a previous-step output driving circuit which sequentially receives the output signals of the plurality of clocked sense amplifiers, delays the output signals of the plurality of clocked sense amplifiers by a predetermined time period, and then intercepts an output of the clocked sense amplifier of a previous step.

摘要翻译： 一种半导体存储器件，包括位线读出放大器，用于放大与存储在存储单元的电容器中的电荷相对应的电压并输出放大电压;以及I / O读出放大器，用于接收位线读出放大器的输出，放大 公开了输出的电压电平并输出放大的电压电平。 半导体存储器件包括读出放大使能信号控制部分，其接收初始读出放大使能信号，将初始读出放大使能信号顺序地延迟多个预定时间周期，并且选择性地输出多个延迟读出放大使能信号， 半导体存储器件的操作速度和制造成品率; 多个时钟读出放大器，其各自接收I / O读出放大器的输出信号，响应于多个延迟读出放大使能信号中的每一个放大I / O读出放大器的输出信号，并依次输出输出 电源电压信号或接地电压电平响应; 以及前级输出驱动电路，其依次接收多个时钟读出放大器的输出信号，将多个时钟读出放大器的输出信号延迟预定的时间周期，然后截取时钟感测放大器的输出 前一步。

公开(公告)号：US08416632B2

公开(公告)日：2013-04-09

申请号：US12904302

申请日：2010-10-14

申请人： Ki-Heung Kim ,  Seong-Jin Jang ,  Myeong-O Kim ,  Hong-Jun Lee ,  Tae-Yoon Lee

发明人： Ki-Heung Kim ,  Seong-Jin Jang ,  Myeong-O Kim ,  Hong-Jun Lee ,  Tae-Yoon Lee

IPC分类号： G11C5/14

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/1204

摘要： A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.

摘要翻译： 位线预充电电压发生器包括漏电修整单元和位线预充电电压提供单元。 泄漏修整单元向输出节点施加泄漏电流以将位线预充电电压置于死区的边缘。 位线预充电电压提供单元向输出节点提供位线预充电电压，并将位线预充电电压设置为目标电平。 位线预充电电压发生器产生具有包括死区的分布的位线预充电电压。

公开(公告)号：US08107308B2

公开(公告)日：2012-01-31

申请号：US12686176

申请日：2010-01-12

申请人： Myeong-O Kim ,  Jae-Won Ko ,  Reum Oh

发明人： Myeong-O Kim ,  Jae-Won Ko ,  Reum Oh

IPC分类号： G11C7/06 ,  G11C8/10

CPC分类号： G11C11/4096 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/002

摘要： A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the bit-line pairs to a sensing voltage level. A command decoder decodes a command applied from the outside and outputs the decoded command. A plurality of input/output (I/O) gates electrically connects the bit-line pairs with corresponding I/O line pairs in response to a voltage level applied through a plurality of corresponding column selection lines. A column decoder decodes a column address and drives at least one of the column selection lines to a plurality of different voltages levels.

摘要翻译： 提供半导体存储器件。 存储单元阵列具有连接在多个字线和多个位线对之间的多个存储单元。 读出放大器单元具有分别与位线对连接的多个读出放大器，并将位线对的数据放大到感测电压电平。 命令解码器解码从外部施加的命令并输出解码的命令。 响应于通过多个相应的列选择线施加的电压电平，多个输入/输出（I / O）门将位线对与对应的I / O线对电连接。 列解码器解码列地址并将列选择线中的至少一个驱动到多个不同的电压电平。

公开(公告)号：US07872932B2

公开(公告)日：2011-01-18

申请号：US12187269

申请日：2008-08-06

申请人： Myeong-O Kim ,  Byung-Chul Kim ,  Yong-Gyu Chu

发明人： Myeong-O Kim ,  Byung-Chul Kim ,  Yong-Gyu Chu

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C7/12 ,  G11C8/18

摘要： A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The semiconductor memory device may include a precharge unit configured to generate a plurality of precharge signals and a controller configured to control precharging of the at least one local input/output line responsive to block information corresponding to activation of at least one of the memory cell array blocks and responsive to at least one of the precharge signals.

摘要翻译： 一种用于对本地输入/输出线进行预充电的方法和半导体存储器件。 可以具有开放位线结构的半导体存储器件通过耦合到第一至第n存储器单元阵列块（n为自然数）的位线的本地输入/输出线传输数据。 半导体存储器件可以包括：预充电单元，其被配置为产生多个预充电信号;以及控制器，被配置为响应于对应于至少一个存储单元阵列的激活来控制至少一个本地输入/输出线的预充电 并且响应于至少一个预充电信号。

公开(公告)号：US20100177582A1

公开(公告)日：2010-07-15

申请号：US12686176

申请日：2010-01-12

申请人： Myeong-O Kim ,  Jae-Won Ko ,  Reum Oh

发明人： Myeong-O Kim ,  Jae-Won Ko ,  Reum Oh

IPC分类号： G11C7/06 ,  G11C8/10 ,  G11C8/08 ,  G11C5/14

CPC分类号： G11C11/4096 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/002

摘要： A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the bit-line pairs to a sensing voltage level. A command decoder decodes a command applied from the outside and outputs the decoded command. A plurality of input/output (I/O) gates electrically connects the bit-line pairs with corresponding I/O line pairs in response to a voltage level applied through a plurality of corresponding column selection lines. A column decoder decodes a column address and drives at least one of the column selection lines to a plurality of different voltages levels.

摘要翻译： 提供半导体存储器件。 存储单元阵列具有连接在多个字线和多个位线对之间的多个存储单元。 读出放大器单元具有分别与位线对连接的多个读出放大器，并将位线对的数据放大到感测电压电平。 命令解码器解码从外部施加的命令并输出解码的命令。 响应于通过多个相应的列选择线施加的电压电平，多个输入/输出（I / O）门将位线对与对应的I / O线对电连接。 列解码器解码列地址并将列选择线中的至少一个驱动到多个不同的电压电平。

公开(公告)号：US07259595B2

公开(公告)日：2007-08-21

申请号：US11120804

申请日：2005-05-02

申请人： Myeong-O Kim

发明人： Myeong-O Kim

IPC分类号： G01R23/02

CPC分类号： G11C29/50012 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02

摘要： A frequency detection circuit and method of detecting the frequency of a clock signal, and a latency signal generation circuit for a semiconductor memory device that includes the frequency detection circuit. The frequency detection circuit includes a frequency detector and an output controller, which determines whether or not the frequency of the clock signal is higher than a predetermined value. Embodiments of the invention have an increased accuracy, increased efficiency, and a reduced current consumption over conventional art.

摘要翻译： 检测时钟信号的频率的频率检测电路和方法，以及包括频率检测电路的半导体存储器件的等待时间信号产生电路。 频率检测电路包括频率检测器和输出控制器，其确定时钟信号的频率是否高于预定值。 与常规技术相比，本发明的实施例具有增加的精度，增加的效率和降低的电流消耗。

公开(公告)号：US20060146619A1

公开(公告)日：2006-07-06

申请号：US11327247

申请日：2006-01-05

申请人： Min-Soo Kim ,  Myeong-O Kim ,  Jae-Woong Lee

发明人： Min-Soo Kim ,  Myeong-O Kim ,  Jae-Woong Lee

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C7/22 ,  G11C8/18

CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A control unit for a semiconductor memory device, a semiconductor memory device and a method for controlling the same. The control unit of a semiconductor memory device includes control signal circuits, each control signal circuit to receive a master signal and to generate at least one of a plurality of control signals in response to the master signal, each of the plurality of core control signals to be generated after a delay specific to the core control signals after a transition of the master signal, the plurality of control signals to control the semiconductor memory device.

摘要翻译： 一种用于半导体存储器件的控制单元，半导体存储器件及其控制方法。 半导体存储器件的控制单元包括控制信号电路，每个控制信号电路接收主信号并响应于主信号产生多个控制信号中的至少一个，多个核心控制信号中的每一个至 在主信号转换之后的核心控制信号的特定延迟之后产生多个控制信号以控制半导体存储器件。

公开(公告)号：US07570529B2

公开(公告)日：2009-08-04

申请号：US11830142

申请日：2007-07-30

申请人： Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

发明人： Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/005

摘要： A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal. The calibration circuit includes a switch element that is connected between the output terminal of the first inverter and the bit line and is turned on or off in response to a calibration control signal.

摘要翻译： 半导体存储器件的读出放大器电路及其操作方法，其中读出放大器电路包括与位线连接的位线读出放大器，以检测和放大位线的信号，校准电路校准 基于位线读出放大器的逻辑阈值的位线的电压电平。 位线检测放大器在校准位线的电压电平后，感测并放大位线的信号。 位线读出放大器可以包括2级级联锁存器，其包括具有与位线连接的输入端的第一反相器; 以及第二反相器，其具有与第一反相器的输出端子连接的输入端子和与位线连接的输出端子，并且响应于感测控制信号而被允许/禁止。 校准电路包括开关元件，其连接在第一反相器的输出端和位线之间，并响应于校准控制信号而导通或截止。