A control unit for a semiconductor memory device, a semiconductor memory device and a method for controlling the same. The control unit of a semiconductor memory device includes control signal circuits, each control signal circuit to receive a master signal and to generate at least one of a plurality of control signals in response to the master signal, each of the plurality of core control signals to be generated after a delay specific to the core control signals after a transition of the master signal, the plurality of control signals to control the semiconductor memory device.