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    Ultra low deposition rate PECVD silicon nitride
    1.
    发明授权
    Ultra low deposition rate PECVD silicon nitride 有权
    超低沉积速率PECVD氮化硅

    公开(公告)号：US06686232B1

    公开(公告)日：2004-02-03

    申请号：US10173717

    申请日：2002-06-19

    申请人： Minh Van Ngo ,  Robert A. Huertas ,  Dawn Hopper ,  Hieu Pham

    发明人： Minh Van Ngo ,  Robert A. Huertas ,  Dawn Hopper ,  Hieu Pham

    IPC分类号： H01L21471

    CPC分类号： H01L29/6659 ,  C23C16/345 ,  H01L21/3185 ,  H01L29/6656

    摘要： A thin silicon nitride layer is deposited at an ultra low deposition rate by PECVD by reducing the NH3 flow rate and/or reducing the SiH4 flow rate. Embodiments include depositing a thin layer of silicon nitride, e.g., 100 Å or less, on a thin silicon oxide liner over a gate electrode, at an NH3 flow rate of 100 to 800 sccm, a SiH4 flow rate of 50 to 100 sccm and a reduced pressure of 0.8 to 1.8 Torr. Embodiments of the present invention further include depositing the silicon nitride layer in multiple deposition stages, e.g., depositing the silicon nitride layer in five deposition stages of 20 Å each.

    摘要翻译： 通过减少NH 3流速和/或降低SiH 4流速，通过PECVD以超低沉积速率沉积薄的氮化硅层。 实施例包括在栅电极上的薄氧化硅衬垫上以100至800sccm的NH 3流速，50至100sccm的SiH 4流率和50至100sccm的SiH 4流速沉积例如100或更小的氮化硅薄层 0.8〜1.8乇减压。 本发明的实施例还包括在多个沉积阶段中沉积氮化硅层，例如，将氮化硅层沉积在各自的五个沉积阶段中。

    Conformal liner for gap-filling
    4.
    发明申请
    Conformal liner for gap-filling 审中-公开
    用于间隙填充的保形衬套

    公开(公告)号：US20080096364A1

    公开(公告)日：2008-04-24

    申请号：US11582442

    申请日：2006-10-18

    申请人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    发明人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823468 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823437

    摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

    摘要翻译： 通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。 实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域 ，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。 实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。

    Gap-filling with uniform properties
    6.
    发明授权
    Gap-filling with uniform properties 有权
    间隙填充均匀性

    公开(公告)号：US08415256B1

    公开(公告)日：2013-04-09

    申请号：US12982364

    申请日：2010-12-30

    申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

    摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

    摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。

    Gap-filling with uniform properties
    8.
    发明授权
    Gap-filling with uniform properties 有权
    间隙填充均匀性

    公开(公告)号：US07884030B1

    公开(公告)日：2011-02-08

    申请号：US11408086

    申请日：2006-04-21

    申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L23/58

    CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

    摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

    摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。

    Method of treating inlaid copper for improved capping layer adhesion without damaging porous low-k materials
    10.
    发明授权
    Method of treating inlaid copper for improved capping layer adhesion without damaging porous low-k materials 失效
    处理镶嵌铜以改善覆盖层粘合而不损害多孔低k材料的方法

    公开(公告)号：US06875694B1

    公开(公告)日：2005-04-05

    申请号：US10774418

    申请日：2004-02-10

    申请人： Minh Van Ngo ,  Robert Huertas ,  Hieu Pham

    发明人： Minh Van Ngo ,  Robert Huertas ,  Hieu Pham

    IPC分类号： H01L21/44 ,  H01L21/768

    CPC分类号： H01L21/76834 ,  H01L21/76807 ,  H01L21/76877

    摘要： An exposed surface of inlaid Cu is plasma treated for improved capping layer adhesion while controlling plasma conditions to avoid damaging porous low-k materials. Embodiments include forming a dual damascene opening in a porous dielectric material having a dielectric constant (k) of up to 2.4, e.g., 2.0 to 2.2, filling the opening with Cu, conducting CMP, plasma treating the exposed Cu surface in NH3 or H2 at a low power, e.g., 75 to 125 watts, for a short period of time, e.g., 2 to 8 seconds, without etching the porous low-k material and depositing a capping layer, e.g., silicon nitride or silicon carbide.

    摘要翻译： 嵌入的Cu的暴露表面被等离子体处理以改善覆盖层粘合，同时控制等离子体条件以避免损坏多孔低k材料。 实施例包括在具有高达2.4的介电常数（k）的多孔电介质材料中形成双镶嵌开口，例如2.0至2.2，用Cu填充开口，进行CMP，等离子体处理在NH 3或H 2中暴露的Cu表面 低功率，例如75至125瓦，短时间，例如2至8秒，而不蚀刻多孔低k材料并沉积覆盖层，例如氮化硅或碳化硅。