公开(公告)号：US20170256527A1

公开(公告)日：2017-09-07

申请号：US15600526

申请日：2017-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wataru Tsukada ,  Masayuki Honda ,  Yoshihisa Fukushima ,  Scott Richard Cyr

IPC: H01L25/18 ,  G11C5/04 ,  G11C5/06 ,  H01L25/065

CPC classification number: H01L25/18 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C29/025 ,  G11C29/50008 ,  G11C2207/105 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.

公开(公告)号：US10199363B2

公开(公告)日：2019-02-05

申请号：US15600526

申请日：2017-05-19

Applicant: Micron Technology, Inc.

Inventor： Wataru Tsukada ,  Masayuki Honda ,  Yoshihisa Fukushima ,  Scott Richard Cyr

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  G11C29/02 ,  G11C29/50 ,  G11C7/10

Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.

公开(公告)号：US09691744B2

公开(公告)日：2017-06-27

申请号：US14839771

申请日：2015-08-28

Applicant: Micron Technology, Inc.

Inventor： Wataru Tsukada ,  Masayuki Honda ,  Yoshihisa Fukushima ,  Scott Richard Cyr

IPC: H01L23/13 ,  H01L25/18 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  G11C29/02 ,  G11C29/50 ,  G11C7/10 ,  H01L23/538

CPC classification number: H01L25/18 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C29/025 ,  G11C29/50008 ,  G11C2207/105 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.

公开(公告)号：US11107507B2

公开(公告)日：2021-08-31

申请号：US16448541

申请日：2019-06-21

Applicant: Micron Technology, Inc.

Inventor： Yogesh Sharma ,  Atsushi Morishima ,  Yoshihisa Fukushima

IPC: G11C5/06 ,  H05K1/02 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096

Abstract: Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).

公开(公告)号：US20160064366A1

公开(公告)日：2016-03-03

申请号：US14839771

申请日：2015-08-28

Applicant: Micron Technology, Inc.

Inventor： Wataru Tsukada ,  Masayuki Honda ,  Yoshihisa Fukushima ,  Scott Richard Cyr

IPC: H01L25/18 ,  G11C5/02 ,  H01L23/522 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C29/025 ,  G11C29/50008 ,  G11C2207/105 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.

Abstract translation: 半导体模块包括模块基板，提供给模块基板的线图案，模块基板上的第一和第二半导体芯片，并且耦合到线图案，以及模块基板上的端接电阻并耦合到线路图案，终端 电阻器位于第一和第二半导体芯片之间。

公开(公告)号：US12181948B2

公开(公告)日：2024-12-31

申请号：US17936083

申请日：2022-09-28

Applicant: Micron Technology, Inc.

Inventor： William A. Lendvay ,  Paul Zipp ,  Yoshihisa Fukushima ,  Mamoru Nagase ,  Tetsuya Shibata

IPC: G06F1/32 ,  G06F1/3234 ,  G11C5/14

Abstract: Methods, systems, and devices for programming power management circuits in a system are described. An apparatus may include a set of one or more power management circuits configured to provide one or more operating voltages for the apparatus. The apparatus may also include an interface coupled with a controller via a bus. The apparatus may include a first switching circuit configured to isolate the bus from the controller and to couple the bus with a second switching circuit. The second switching circuit may be configured to isolate the set of one or more power management circuits from the controller and to couple the set of one or more power management circuits with the first switching circuit.

公开(公告)号：US20240103599A1

公开(公告)日：2024-03-28

申请号：US17936083

申请日：2022-09-28

Applicant: Micron Technology, Inc.

Inventor： William A. Lendvay ,  Paul Zipp ,  Yoshihisa Fukushima ,  Mamoru Nagase ,  Tetsuya Shibata

IPC: G06F1/3234 ,  G11C5/14

CPC classification number: G06F1/3253 ,  G06F1/3275 ,  G11C5/14

Abstract: Methods, systems, and devices for programming power management circuits in a system are described. An apparatus may include a set of one or more power management circuits configured to provide one or more operating voltages for the apparatus. The apparatus may also include an interface coupled with a controller via a bus. The apparatus may include a first switching circuit configured to isolate the bus from the controller and to couple the bus with a second switching circuit. The second switching circuit may be configured to isolate the set of one or more power management circuits from the controller and to couple the set of one or more power management circuits with the first switching circuit.

公开(公告)号：US20210358526A1

公开(公告)日：2021-11-18

申请号：US17443673

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yogesh Sharma ,  Atsushi Morishima ,  Yoshihisa Fukushima

IPC: G11C5/06 ,  H05K1/02 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096

Abstract: Apparatuses and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane.

公开(公告)号：US20250093938A1

公开(公告)日：2025-03-20

申请号：US18965803

申请日：2024-12-02

Applicant: Micron Technology, Inc.

Inventor： William A. Lendvay ,  Paul Zipp ,  Yoshihisa Fukushima ,  Mamoru Nagase ,  Tetsuya Shibata

IPC: G06F1/3234 ,  G11C5/14

Abstract: Methods, systems, and devices for programming power management circuits in a system are described. An apparatus may include a set of one or more power management circuits configured to provide one or more operating voltages for the apparatus. The apparatus may also include an interface coupled with a controller via a bus. The apparatus may include a first switching circuit configured to isolate the bus from the controller and to couple the bus with a second switching circuit. The second switching circuit may be configured to isolate the set of one or more power management circuits from the controller and to couple the set of one or more power management circuits with the first switching circuit.