MOISTURE RESISTANT SEMICONDUTOR DEVICE

    公开(公告)号:US20250140713A1

    公开(公告)日:2025-05-01

    申请号:US18673383

    申请日:2024-05-24

    Abstract: A moisture resistant semiconductor device may include a substrate and a plurality of terminations in the substrate of the semiconductor device, wherein the plurality of terminations are laterally adjacent to an active region of the semiconductor device. A first insulating layer which overlays the plurality of terminations and the substrate. A trench into the substrate located laterally beyond an edge of the plurality of terminations. A contact layer which overlays the first insulating layer. A second insulating layer which overlays the contact layer. The second insulating layer which overlays the trench. A third insulating layer which overlays the second insulating layer.

    Interconnect monitor utilizing both open and short detection

    公开(公告)号:US10177053B2

    公开(公告)日:2019-01-08

    申请号:US15447656

    申请日:2017-03-02

    Inventor: Randy L. Yach

    Abstract: The present disclosure relates to semiconductor manufacturing and the teachings of the present disclosure may be embodied in a semiconductor chip with an interconnect monitor. Some embodiments may include arrays of diodes on the semiconductor chip; each diode with a stack of vertical interconnects and metal contacts, the stack and the diode connected in series and control mechanisms for addressing the diodes. The control mechanisms may include first inverters for applying either a high or a low voltage to columns of the diode stacks, connected at one end of each diode stack. Each first inverter may include reverse logic receiving a reverse logic signal and configured to invert a logic signal fed to the device for applying a relatively high or low voltage and second inverters for applying either a high or a low voltage to rows of the diode stack in the one of the plurality of arrays, connected at a second end of said diode stack, wherein each second inverter comprises reverse logic receiving an inverted reverse logic signal and configured to invert a logic signal fed to the device for applying a relatively high or low voltage.

    TRANSISTOR AND METHOD FOR MANUFACTURING SAME

    公开(公告)号:US20250120145A1

    公开(公告)日:2025-04-10

    申请号:US18736957

    申请日:2024-06-07

    Abstract: A transistor that may include a substrate, a drain layer formed within the substrate at a first side of the substrate. A first well implant having a first implant depth, a second well implant having a second implant depth and a third well implant having a third implant depth. The first well implant, the second well implant and the third well implant formed within the substrate at the second side of the substrate. The second implant depth is greater than the first implant depth and the third implant depth is greater than the second implant depth. A gate formed at the second side of the substrate. The gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance and the gate overlaps the third well implant by a third distance.

    Interconnect Monitor Utilizing Both Open And Short Detection

    公开(公告)号:US20170256469A1

    公开(公告)日:2017-09-07

    申请号:US15447656

    申请日:2017-03-02

    Inventor: Randy L. Yach

    CPC classification number: H01L22/34 H01L21/67288 H01L22/30 H01L22/32

    Abstract: The present disclosure relates to semiconductor manufacturing and the teachings of the present disclosure may be embodied in a semiconductor chip with an interconnect monitor. Some embodiments may include arrays of diodes on the semiconductor chip; each diode with a stack of vertical interconnects and metal contacts, the stack and the diode connected in series and control mechanisms for addressing the diodes. The control mechanisms may include first inverters for applying either a high or a low voltage to columns of the diode stacks, connected at one end of each diode stack. Each first inverter may include reverse logic receiving a reverse logic signal and configured to invert a logic signal fed to the device for applying a relatively high or low voltage and second inverters for applying either a high or a low voltage to rows of the diode stack in the one of the plurality of arrays, connected at a second end of said diode stack, wherein each second inverter comprises reverse logic receiving an inverted reverse logic signal and configured to invert a logic signal fed to the device for applying a relatively high or low voltage.

    Integrated Circuit With Sensor Printed In Situ
    7.
    发明申请
    Integrated Circuit With Sensor Printed In Situ 审中-公开
    传感器原位集成电路

    公开(公告)号:US20160360622A1

    公开(公告)日:2016-12-08

    申请号:US15169456

    申请日:2016-05-31

    Abstract: The present disclosure teaches a method for manufacturing a module comprising an integrated circuit and a sensor. The method may comprise: mounting an integrated circuit (IC) die on a printed circuit board (PCB) using a high temperature process to provide an electrical connection between interconnects of the PCB and the die; and printing a sensor directly onto the module after all high temperature mounting processes are complete.

    Abstract translation: 本公开教导了一种用于制造包括集成电路和传感器的模块的方法。 该方法可以包括:使用高温处理将集成电路(IC)管芯安装在印刷电路板(PCB)上,以提供PCB与管芯的互连之间的电连接; 并在所有高温安装过程完成后将传感器直接打印到模块上。

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