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    Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs
    1.
    发明授权
    Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs 有权
    锁相环和延迟锁定环包括具有差分控制输入的差分延迟单元

    公开(公告)号：US07176737B2

    公开(公告)日：2007-02-13

    申请号：US10876730

    申请日：2004-06-25

    申请人： Michael P. Baker ,  Steven C. Meyers

    发明人： Michael P. Baker ,  Steven C. Meyers

    IPC分类号： H03H11/26

    CPC分类号： H03L7/0995 ,  H03F2203/45362 ,  H03F2203/45466 ,  H03F2203/45644 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03L7/0812

    摘要： A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.

    摘要翻译： 本文提供了一种差分延迟单元，其不仅接收一对差分输入值，而且还接收一对差分控制值，用于延迟差分输入值以产生一对差分输出值。 因此，提供了一种真正差分的延迟单元，因此能够显着地提高噪声性能。 本发明的差分延迟单元还表现出围绕中心频率，恒定增益和增加的调谐范围能力的高频稳定性。 以这种方式，差分延迟单元可以分别用在PLL或DLL设计中，作为低噪声VCO或低噪声延迟线的一部分。

    Circuits, architectures and methods for detecting and correcting excess oscillator frequencies
    3.
    发明授权
    Circuits, architectures and methods for detecting and correcting excess oscillator frequencies 有权
    用于检测和校正多余振荡器频率的电路，结构和方法

    公开(公告)号：US6140880A

    公开(公告)日：2000-10-31

    申请号：US159908

    申请日：1998-09-24

    申请人： Nathan Y. Moyal ,  Mark J. Marlett ,  Steven C. Meyers

    发明人： Nathan Y. Moyal ,  Mark J. Marlett ,  Steven C. Meyers

    IPC分类号： H03L7/089 ,  H03L7/10 ,  H03L7/18 ,  H03L7/00

    CPC分类号： H03L7/10 ,  H03L7/105 ,  H03L7/18 ,  H03L2207/06 ,  H03L7/089

    摘要： A circuit and method for preventing an oscillator from oscillating above a first predetermined frequency or below a second predetermined frequency. The present invention may comprise (a) a clock generation circuit configured to generate an output clock signal in response to (i) a reference clock, (ii) one or more control signals and (ii) a reset signal and (b) a control circuit configured to generate said reset signal in response to said one or more control signals.

    摘要翻译： 一种用于防止振荡器在第一预定频率之上振荡或低于第二预定频率的电路和方法。 本发明可以包括：（a）时钟生成电路，被配置为响应于（i）参考时钟，（ii）一个或多个控制信号和（ii）复位信号而产生输出时钟信号，以及（b）控制 电路，被配置为响应于所述一个或多个控制信号而产生所述复位信号。

    PROGRAMMABLE BANDGAP VOLTAGE REFERENCE
    5.
    发明申请
    PROGRAMMABLE BANDGAP VOLTAGE REFERENCE 审中-公开
    可编程带式电压参考

    公开(公告)号：US20120206192A1

    公开(公告)日：2012-08-16

    申请号：US13027495

    申请日：2011-02-15

    申请人： Jay B. Fletcher ,  Steven C. Meyers

    发明人： Jay B. Fletcher ,  Steven C. Meyers

    IPC分类号： G05F1/10

    CPC分类号： G05F3/30

    摘要： A bandgap reference circuit includes an amplifier configured to provide an output voltage dependent upon voltages appearing at an inverting input and a non-inverting input. The bandgap reference circuit also includes a first transistor coupled between the non-inverting input and a circuit ground reference, and a first resistor coupled to the inverting input. The bandgap reference circuit also includes a number of second transistors coupled in parallel between the circuit ground reference and the first resistor. At least a portion of the second transistors are connected to the first resistor through a plurality of programmably selectable switches.

    摘要翻译： 带隙参考电路包括放大器，其被配置为提供取决于出现在反相输入端和非反相输入端的电压的输出电压。 带隙基准电路还包括耦合在非反相输入端和电路接地基准之间的第一晶体管和耦合到反相输入端的第一电阻器。 带隙基准电路还包括并联在电路接地基准和第一电阻之间的多个第二晶体管。 第二晶体管的至少一部分通过多个可编程选择的开关连接到第一电阻器。

    Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch
    6.
    发明授权
    Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch 有权
    电路，系统和方法，用于可编程地将输入设置为锁存器的优先级排序器以避免锁存器的不期望的输出状态

    公开(公告)号：US06657472B1

    公开(公告)日：2003-12-02

    申请号：US10132857

    申请日：2002-04-25

    申请人： S. Babar Raza ,  Steven C. Meyers

    发明人： S. Babar Raza ,  Steven C. Meyers

    IPC分类号： H03K3037

    CPC分类号： H03K3/0375 ,  H03K3/356034

    摘要： The present invention includes a circuit, system, and method for avoiding a non-desired output from a latch, and a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values. The embodiments described herein are useful in forming a non-clocked latch that employs set and reset inputs, and thus, may be an SR latch. The SR latch is envisioned having either MOSFET or bipolar transistors, and can be employed either having only NMOS transistors, only PMOS transistors, or CMOS transistors. The latch also includes an improved selector circuit that is easily programmed to configure the latch in either a set-dominant, a reset-dominant, or a memory-dominant configuration based solely on the voltage values fed to the latch by the selector circuit. As such, the selector circuit of the present invention embodies an improved programmability over previous circuits.

    摘要翻译： 本发明包括一种用于避免来自锁存器的非期望输出的电路，系统和方法，以及选择器电路，其可编程以选择对优先化器的输入，所述选择器电路基于该输入，设置锁存器输出以避免 不理想的状态，不管锁存输入值如何。 这里描述的实施例在形成采用设置和复位输入的非时钟锁存器中是有用的，因此可以是SR锁存器。 SR锁存器被设想为具有MOSFET或双极晶体管，并且可以采用仅具有NMOS晶体管，仅PMOS晶体管或CMOS晶体管。 锁存器还包括改进的选择器电路，其易于编程以仅基于通过选择器电路馈送到锁存器的电压值来将锁存器配置为集占主导地位，复位占优位或存储器占优配置。 因此，本发明的选择器电路比以前的电路体现了改进的可编程性。

    Programmable latch that avoids a non-desired output state
    7.
    发明授权
    Programmable latch that avoids a non-desired output state 有权
    可编程锁存器，避免不需要的输出状态

    公开(公告)号：US06549050B1

    公开(公告)日：2003-04-15

    申请号：US09951369

    申请日：2001-09-13

    申请人： Steven C. Meyers ,  Terry D. Little

    发明人： Steven C. Meyers ,  Terry D. Little

    IPC分类号： H03K3037

    CPC分类号： H03K3/0375 ,  H03K3/356017

    摘要： A circuit and method are provided for ensuring a non-desired output state of a latch or flip-flop cannot be produced. The latch can be configured as a set dominant, reset dominant, or memory dominant circuit by simply placing programmed voltage values on select transistors of the latch. The programmed values will cause either the set input, the reset input, or both set and reset inputs to have a complimentary effect on the output signals even though the set and reset inputs are at the same logic level. The set, reset, and memory dominant circuit is identical in structure; however, the set, reset, and memory dominant features are derived solely by placing programmed values on corresponding transistors within the identical structure. A generic latch circuit can, therefore, be said to operate in one of three dominant ways depending on the programmed values chosen by a selector and fed to a prioritizer.

    摘要翻译： 提供了一种用于确保不能产生锁存器或触发器的不希望的输出状态的电路和方法。 通过简单地将编程的电压值放置在锁存器的选择晶体管上，可以将锁存器配置为集成主导，复位主导或存储器主导电路。 即使设置和复位输入处于相同的逻辑电平，编程的值将导致设置输入，复位输入或设置和复位输入对输出信号产生互补影响。 设置，复位和存储器主导电路的结构相同; 然而，集成，复位和存储器主要特征仅通过将编程值放置在相同结构内的相应晶体管上而得到。 因此，通常的锁存电路可以根据选择器所选择的编程值，被称为以三种主要方式之一进行操作，并被馈送给优先级调节器。