公开(公告)号：US5751932A

公开(公告)日：1998-05-12

申请号：US485217

申请日：1995-06-07

申请人： Robert W. Horst ,  William Edward Baker ,  Randall G. Banton ,  John Michael Brown ,  William F. Bruckert ,  William Patterson Bunton ,  Gary F. Campbell ,  John Deane Coddington ,  Richard W. Cutts, Jr. ,  Barry Lee Drexler ,  Harry Frank Elrod ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Geoffrey I. Iswandhi ,  Douglas Eugene Jewett ,  Curtis Willard Jones, Jr. ,  James Stevens Klecka ,  John C. Krause ,  Stephen G. Low ,  Susan Stone Meredith ,  Steven C. Meyers ,  David P. Sonnier ,  William Joel Watson ,  Patricia L. Whiteside ,  Frank A. Williams ,  Linda Ellen Zalzala

发明人： Robert W. Horst ,  William Edward Baker ,  Randall G. Banton ,  John Michael Brown ,  William F. Bruckert ,  William Patterson Bunton ,  Gary F. Campbell ,  John Deane Coddington ,  Richard W. Cutts, Jr. ,  Barry Lee Drexler ,  Harry Frank Elrod ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Geoffrey I. Iswandhi ,  Douglas Eugene Jewett ,  Curtis Willard Jones, Jr. ,  James Stevens Klecka ,  John C. Krause ,  Stephen G. Low ,  Susan Stone Meredith ,  Steven C. Meyers ,  David P. Sonnier ,  William Joel Watson ,  Patricia L. Whiteside ,  Frank A. Williams ,  Linda Ellen Zalzala

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 CPU被构造为以两种模式之一操作：两个CPU彼此独立地操作的单工模式，以及CPU以锁步同步操作的双工模式，以基本上执行相同指令流的每条指令 同一时间。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。