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发明授权
US07176737B2 Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs 有权
锁相环和延迟锁定环包括具有差分控制输入的差分延迟单元

Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs
摘要：
A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.
摘要（中）：

本文提供了一种差分延迟单元，其不仅接收一对差分输入值，而且还接收一对差分控制值，用于延迟差分输入值以产生一对差分输出值。 因此，提供了一种真正差分的延迟单元，因此能够显着地提高噪声性能。 本发明的差分延迟单元还表现出围绕中心频率，恒定增益和增加的调谐范围能力的高频稳定性。 以这种方式，差分延迟单元可以分别用在PLL或DLL设计中，作为低噪声VCO或低噪声延迟线的一部分。

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