公开(公告)号：US20070297433A1

公开(公告)日：2007-12-27

申请号：US11426325

申请日：2006-06-26

Applicant: Meng Ting Lin ,  Cheng-Ting Wu

Inventor： Meng Ting Lin ,  Cheng-Ting Wu

IPC: H04L12/56

CPC classification number: G06F13/4059

Abstract: A double buffering device and operating method thereof are provided to provide data to a second device, comprising a controller, a first buffer and a second buffer, a bus and a software unit. The controller controls data access. The first and second buffers coupled to the controller store the data. The bus is coupled to the controller for data delivery. The software unit provides data to the buffers via the bus. In a first mode, the software unit programs the first buffer with the data, the controller synchronizes the data from the first buffer to the second buffer, and the controller copies the data from the second buffer to the second device. In a second mode, the software unit simultaneously programs the first and second buffers with the data, and the controller copies the data from the second buffer to the second device.

Abstract translation: 提供双缓冲设备及其操作方法以向第二设备提供数据，其包括控制器，第一缓冲器和第二缓冲器，总线和软件单元。 控制器控制数据访问。 耦合到控制器的第一和第二缓冲器存储数据。 总线耦合到控制器进行数据传输。 软件单元通过总线向缓冲区提供数据。 在第一模式中，软件单元使用数据对第一缓冲器进行编程，控制器将数据从第一缓冲器同步到第二缓冲器，并且控制器将数据从第二缓冲器复制到第二设备。 在第二模式中，软件单元同时使用数据对第一和第二缓冲器进行编程，并且控制器将数据从第二缓冲器复制到第二设备。

公开(公告)号：US20070013043A1

公开(公告)日：2007-01-18

申请号：US11302736

申请日：2005-12-13

Applicant: Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

Inventor： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC: H01L23/02

CPC classification number: H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.

Abstract translation: 提供了不具有芯的芯片封装，包括图案化电路层，芯片，焊接掩模，模塑料和多个外部端子。 图案化电路层具有彼此相对的第一表面和第二表面。 布置在第一表面上的芯片电连接到图案化电路层。 设置在第二表面上的焊料掩模具有多个第一开口，图案化电路层的一部分露出。 具有多个通孔的成型复合物覆盖图形电路层，并将芯片固定在图案化电路层上。 布置在通孔中的每个外部端子电连接到图案化电路层。

公开(公告)号：US20090189296A1

公开(公告)日：2009-07-30

申请号：US12275172

申请日：2008-11-20

Applicant: Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

Inventor： Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3114 ,  H01L23/49517 ,  H01L23/49822 ,  H01L23/49861 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.

Abstract translation: 提供了一种倒装芯片四边形扁平无铅封装结构的制造方法。 首先在制造方法中设置具有多根引线的引线框架。 在引线框架上形成介电层，并使引线的顶表面和底表面露出。 在电介质层上形成包括多个焊盘的重分配层和连接焊盘和引线顶表面的多条导线。 形成阻焊层以覆盖再分布层，电介质层和引线，并露出焊盘的表面。 在阻焊层上形成粘接层。 提供具有多个凸块的芯片。 该芯片用粘合剂层粘附在阻焊层上，并且每个凸块与其中一个焊盘电连接。

公开(公告)号：US20080281999A1

公开(公告)日：2008-11-13

申请号：US11744961

申请日：2007-05-07

Applicant: Hsin-Yu Kang ,  Cheng-Ting Wu

Inventor： Hsin-Yu Kang ,  Cheng-Ting Wu

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: In an electronic system, a DMA circuit is supplied with a device selection signal that indicates a processor is accessing or going to access a memory. If the DMA circuit finds that the processor is not accessing or not going to access the memory, the DMA circuit starts its DMA operations. Once the DMA circuit finds that the processor is going to access the memory, the DMA circuit stops its DMA operation and return the use of the memory to the processor.

Abstract translation: 在电子系统中，向DMA电路提供指示处理器正在访问或将访问存储器的设备选择信号。 如果DMA电路发现处理器没有访问或不访问存储器，DMA电路将启动其DMA操作。 一旦DMA电路发现处理器要访问存储器，DMA电路停止其DMA操作，并将存储器的使用返回给处理器。

公开(公告)号：US20080174031A1

公开(公告)日：2008-07-24

申请号：US11806023

申请日：2007-05-29

Applicant: Hung-Tsun Lin ,  Wu-Chang Tu ,  Cheng-Ting Wu

Inventor： Hung-Tsun Lin ,  Wu-Chang Tu ,  Cheng-Ting Wu

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/585 ,  H01L24/28 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83138 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.

Abstract translation: IC封装主要包括基板，管芯安装层，芯片，至少一个接合线和多个电连接部件。 基板具有顶表面和底表面，其中顶表面包括用于设置管芯附接层的管芯附着区域。 芯片通过管芯附着层附接到管芯附着区域，并通过电连接部件与衬底电连接。 接合线的两端接合到基板的顶表面上的两个互连指状物，其中至少一部分接合线被封装在管芯附着层中以替代传统衬底内部的一些布线或通孔。 因此，衬底具有简单且降低的布线层，即降低衬底成本。 也显示了相应IC封装的芯片载体。

公开(公告)号：US20070035008A1

公开(公告)日：2007-02-15

申请号：US11322409

申请日：2006-01-03

Applicant: Cheng-Ting Wu ,  Shih-Feng Chiu ,  Tu-Tang Pan ,  Ting-Yuan Chen ,  Yu-Cheng Chang ,  Ming-Hung Su

Inventor： Cheng-Ting Wu ,  Shih-Feng Chiu ,  Tu-Tang Pan ,  Ting-Yuan Chen ,  Yu-Cheng Chang ,  Ming-Hung Su

IPC: H01L23/12 ,  H01L23/053

CPC classification number: H01L23/367 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/544 ,  H01L24/32 ,  H01L24/48 ,  H01L29/0657 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/10155 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A thin IC package to enhance heat dissipation from the back surface of a chip, comprises a substrate, the chip, and an encapsulant where the substrate has an upper surface, a lower surface, and an opening to accommodate the chip. The chip is disposed in the opening of the substrate where the chip has an active surface, a back surface, and a plurality of bonding pads disposed on the active surface to electrically connect to the substrate. At least a slot is formed on the back surface of the chip. Preferably, a plurality of the slots on the back surface of the chip form a plurality of integral thermal fins therefrom. The encapsulant are formed on the upper surface of the substrate and in the opening to embed the chip with the back surface and the slots being exposed from the encapsulant to enhance the heat dissipation from the back surface of the chip and to enhance chip strength.

Abstract translation: 用于增强从芯片背表面散热的薄IC封装包括衬底，芯片和密封剂，其中衬底具有上表面，下表面和容纳芯片的开口。 芯片设置在基板的开口中，其中芯片具有有源表面，背表面和设置在有源表面上以电连接到基板的多个接合焊盘。 在芯片的背面形成有至少一个槽。 优选地，芯片的后表面上的多个槽形成多个与其成一体的散热片。 密封剂形成在基板的上表面和开口中以将芯片与背面嵌入，并且狭缝从密封剂暴露出来，以增强从芯片背面散热并提高芯片强度。

公开(公告)号：US20050094749A1

公开(公告)日：2005-05-05

申请号：US10980074

申请日：2004-11-03

Applicant: Cheng-Ting Wu ,  Hung-Ming Chang

Inventor： Cheng-Ting Wu ,  Hung-Ming Chang

IPC: G06F12/00 ,  H03M13/41 ,  H04L27/06

CPC classification number: H03M13/6505 ,  H03M13/3983 ,  H03M13/41

Abstract: The present invention provides a non-binary Viterbi data processing system comprising a non-binary Viterbi processor, a path metric memory, and a memory access device. The non-binary Viterbi processor is used for obtaining the path metrics of a set of states according to a Viterbi decoding procedure. The path metric memory comprises memory units of the same amount as the states. The memory units are depicted by combinations of symbols for storing the corresponding path metrics of the set of states. The memory access device is used for reading out the path metrics from the path metric memory for calculation by the non-binary Viterbi processor, and for writing the updated path metrics back to the path metric memory. Therefore, merely the same amounts of the memory units as the states in the path metric memory are required for update of the set of path metrics.

Abstract translation: 本发明提供一种非二进制维特比数据处理系统，其包括非二进制维特比处理器，路径度量存储器和存储器访问装置。 非二进制维特比处理器用于根据维特比解码过程获得一组状态的路径度量。 路径度量存储器包括与状态相同量的存储器单元。 存储器单元由用于存储该组状态的相应路径度量的符号的组合来描绘。 存储器访问装置用于从路径度量存储器读出用于由非二进制维特比处理器计算的路径度量，并用于将更新的路径度量写回到路径度量存储器。 因此，仅需要与路径度量存储器中的状态相同量的存储器单元来更新路径度量集合。

公开(公告)号：US20050010314A1

公开(公告)日：2005-01-13

申请号：US10852161

申请日：2004-05-25

Applicant: Cheng-Ting Wu ,  Hung-Ming Chang ,  I-Hung Hsieh

Inventor： Cheng-Ting Wu ,  Hung-Ming Chang ,  I-Hung Hsieh

IPC: H04S1/00 ,  G06F17/00 ,  H03G3/00

CPC classification number: H04S1/007

Abstract: The present invention relates to an audio data synthesis system for sequentially processing a first predetermined number of audio data to synthesize a digital audio signal cumulatively. The system comprises a first memory, a first processor, an audio data processing unit, and a second memory. The first memory is for storing a plurality of audio data. The first processor is for generating an audio processing request for requesting to process a second predetermined number of audio data. The audio data processing unit is for receiving the audio processing request, accessing the second predetermined number of audio data stored in the first memory, and calculating every two neighboring audio data to get data processing values, and after calculating all the second predetermined number of audio data, then obtaining a third predetermined number of data processing values. The second memory is for storing the third predetermined number of audio data.

Abstract translation: 本发明涉及一种音频数据合成系统，用于顺序地处理第一预定数量的音频数据以累积地合成数字音频信号。 该系统包括第一存储器，第一处理器，音频数据处理单元和第二存储器。 第一存储器用于存储多个音频数据。 第一处理器用于产生用于请求处理第二预定数量的音频数据的音频处理请求。 音频数据处理单元用于接收音频处理请求，访问存储在第一存储器中的第二预定数量的音频数据，并计算每两个相邻音频数据以获得数据处理值，并且在计算所有第二预定数量的音频之后 数据，然后获得第三预定数量的数据处理值。 第二存储器用于存储第三预定数量的音频数据。

公开(公告)号：US07939950B2

公开(公告)日：2011-05-10

申请号：US12269112

申请日：2008-11-12

Applicant: Cheng-Ting Wu ,  I-Cheng Lu ,  Yu-Cheng Chang ,  Tsu-Ting Wang

Inventor： Cheng-Ting Wu ,  I-Cheng Lu ,  Yu-Cheng Chang ,  Tsu-Ting Wang

IPC: H01L23/34 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package structure is provided. The chip package structure comprises a first substrate, a second substrate and a plurality of chips. Therein, one of the chips is connected to the first substrate and electrically connected to the first substrate through a via hole of the first substrate. Thereby, the second substrate does not need the via hole for electrical connection of chips and thus, the surface thereof is adapted to remain intact to allow for the disposition of conductive balls throughout the surface.

Abstract translation: 提供了芯片封装结构。 芯片封装结构包括第一衬底，第二衬底和多个芯片。 其中，一个芯片连接到第一基板，并通过第一基板的通孔与第一基板电连接。 因此，第二基板不需要用于芯片电连接的通孔，因此，其表面适于保持完整，以允许在整个表面上布置导电球。

公开(公告)号：US20100187692A1

公开(公告)日：2010-07-29

申请号：US12756377

申请日：2010-04-08

Applicant: Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

Inventor： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC: H01L23/498

CPC classification number: H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract translation: 提供了包括基底，芯片，模塑料和多个外部端子的芯片封装。 该基底基本上由具有彼此相对的第一表面和第二表面的图案化电路层和设置在第二表面上的焊接掩模组成，其中该焊接掩模具有多个第一开口，通过该多个第一开口部分图案化电路层 被暴露。 芯片设置在第一表面上并且电连接到图案化电路层。 模塑料覆盖图案电路层并将芯片固定在图案化电路层上。 外部端子设置在第一开口中并电连接到图案化电路层。