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公开(公告)号：US10128862B2
公开(公告)日：2018-11-13
申请号：US15401106
申请日：2017-01-09
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
Abstract: A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) including: a comparing module and a calibration circuit. The comparing module is arranged to generate a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and a second result by comparing the input voltage value with a second voltage value; the calibration circuit coupled to the comparing module is for generating a determination result determining whether the input voltage value is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result.
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公开(公告)号：US20170244424A1
公开(公告)日：2017-08-24
申请号：US15506234
申请日：2015-08-27
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
Abstract: A hybrid analog-to-digital converter (ADC) includes a plurality of analog-to-digital conversion circuits and a combining circuit. The analog-to-digital conversion circuits generate a plurality of partial digital outputs for a same analog input, respectively, wherein the analog-to-digital conversion circuits include a digital slope ADC used to perform signal quantization in a time domain. The combining circuit combines the partial digital outputs generated from the analog-to-digital conversion circuits to generate a final digital output of the analog input.
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公开(公告)号：US20170214411A1
公开(公告)日：2017-07-27
申请号：US15401106
申请日：2017-01-09
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
CPC classification number: H03M1/1009 , H03M1/001 , H03M1/0692 , H03M1/1042 , H03M1/164 , H03M1/38 , H03M1/468
Abstract: A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) including: a comparing module and a calibration circuit. The comparing module is arranged to generate a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and a second result by comparing the input voltage value with a second voltage value; the calibration circuit coupled to the comparing module is for generating a determination result determining whether the input voltage value is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result.
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公开(公告)号：US10454435B2
公开(公告)日：2019-10-22
申请号：US15830355
申请日：2017-12-04
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
Abstract: A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase.
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公开(公告)号：US09847790B2
公开(公告)日：2017-12-19
申请号：US15506234
申请日：2015-08-27
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
Abstract: A hybrid analog-to-digital converter (ADC) includes a plurality of analog-to-digital conversion circuits and a combining circuit. The analog-to-digital conversion circuits generate a plurality of partial digital outputs for a same analog input, respectively, wherein the analog-to-digital conversion circuits include a digital slope ADC used to perform signal quantization in a time domain. The combining circuit combines the partial digital outputs generated from the analog-to-digital conversion circuits to generate a final digital output of the analog input.
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Patent Agency Ranking
公开(公告)号：US10771078B2
公开(公告)日：2020-09-08
申请号：US16378759
申请日：2019-04-09
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
Abstract: A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.
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公开(公告)号：US10110242B2
公开(公告)日：2018-10-23
申请号：US15830327
申请日：2017-12-04
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
Abstract: An interleaving successive approximation analog-to-digital converter (SAR ADC) with noise shaping having a first SAR block, a second SAR block, and a noise-shaping circuit is provided. The first and second SAR blocks take turns to sample an input voltage for successive approximation of the input voltage and observation of a digital representation of the input voltage. The noise-shaping circuit receives a first residue voltage from the first SAR block and receives a second residue voltage from the second SAR block alternately, and outputs a noise-shaping signal to be fed into the first SAR block and the second SAR block.
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公开(公告)号：US20180183394A1
公开(公告)日：2018-06-28
申请号：US15830355
申请日：2017-12-04
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
Abstract: A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase.
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公开(公告)号：US10003348B2
公开(公告)日：2018-06-19
申请号：US15684285
申请日：2017-08-23
Applicant: MEDIATEK INC.
Inventor： Chun-Cheng Liu
Abstract: An analog-to-digital converter (ADC) using an amplifier-based noise shaping circuit. The amplifier-based noise shaping circuit generates a noise shaping signal. A comparator of the ADC has a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input, a second input terminal receiving the noise shaping signal, and an output terminal for observation of the digital representation of the analog input. The amplifier-based noise shaping circuit uses an amplifier to amplify a residual voltage obtained from the capacitive data acquisition converter and provides a switched capacitor network between the amplifier and the comparator for sampling the amplified residual voltage and generating the noise shaping signal.
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公开(公告)号：US09287891B1
公开(公告)日：2016-03-15
申请号：US14693183
申请日：2015-04-22
Applicant: MediaTek Inc.
Inventor： Zwei-Mei Lee , Chun-Cheng Liu
CPC classification number: H03M1/468 , H03M1/0641 , H03M1/1004 , H03M1/1009 , H03M1/38 , H03M1/40 , H03M1/403
Abstract: A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.
Abstract translation: 提供了一个SAR ADC。 DAC根据模拟输入信号，最高有效位电容和小于最高有效位电容的多个有效位电容提供中间模拟信号。 第一开关电容器阵列根据选择信号选择性地提供最高有效位电容或有效位电容。 有效位电容的总和等于最高有效位电容。 当第一开关电容器阵列提供最高有效位电容时，第二开关电容器阵列提供有效位电容，并且当第一开关电容器阵列提供有效位电容时提供最高有效位电容。 比较器根据中间模拟信号提供比较结果。 SAR逻辑根据比较结果提供数字输出信号。
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