公开(公告)号：US09904752B2

公开(公告)日：2018-02-27

申请号：US14986275

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Zwei-Mei Lee ,  Bo-Jr Huang ,  Chi-Jih Shih ,  Jia-Wei Fang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5009 ,  G06F17/505 ,  G06F2217/78

Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

公开(公告)号：US09287891B1

公开(公告)日：2016-03-15

申请号：US14693183

申请日：2015-04-22

Applicant: MediaTek Inc.

Inventor： Zwei-Mei Lee ,  Chun-Cheng Liu

IPC: H03M1/38 ,  H03M1/46 ,  H03M1/40 ,  H03M1/10

CPC classification number: H03M1/468 ,  H03M1/0641 ,  H03M1/1004 ,  H03M1/1009 ,  H03M1/38 ,  H03M1/40 ,  H03M1/403

Abstract: A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

Abstract translation: 提供了一个SAR ADC。 DAC根据模拟输入信号，最高有效位电容和小于最高有效位电容的多个有效位电容提供中间模拟信号。 第一开关电容器阵列根据选择信号选择性地提供最高有效位电容或有效位电容。 有效位电容的总和等于最高有效位电容。 当第一开关电容器阵列提供最高有效位电容时，第二开关电容器阵列提供有效位电容，并且当第一开关电容器阵列提供有效位电容时提供最高有效位电容。 比较器根据中间模拟信号提供比较结果。 SAR逻辑根据比较结果提供数字输出信号。