TEMPLATE SUBSTRATE AND METHOD FOR MANUFACTURING SAME
    1.
    发明申请
    TEMPLATE SUBSTRATE AND METHOD FOR MANUFACTURING SAME 有权
    模板基板及其制造方法

    公开(公告)号:US20130001753A1

    公开(公告)日:2013-01-03

    申请号:US13423043

    申请日:2012-03-16

    IPC分类号: H01L29/06 H01L21/30

    摘要: According to one embodiment, a template substrate includes a substrate and a mask. The substrate includes a mesa region formed in a central portion of an upper surface of the substrate. The mesa region is configured to protrude more than a region of the substrate around the mesa region. An impurity is introduced into an upper layer portion of a partial region of a peripheral portion of the mesa region. The mask film is provided on the upper surface of the substrate.

    摘要翻译: 根据一个实施例,模板衬底包括衬底和掩模。 衬底包括形成在衬底的上表面的中心部分中的台面区域。 所述台面区域被构造为在所述台面区域周围突出多于所述基板的区域。 杂质被引入到台面区域的周边部分的部分区域的上层部分中。 掩模膜设置在基板的上表面上。

    Template substrate, method for manufacturing same, and template
    3.
    发明授权
    Template substrate, method for manufacturing same, and template 有权
    模板基板,其制造方法和模板

    公开(公告)号:US09377682B2

    公开(公告)日:2016-06-28

    申请号:US13423043

    申请日:2012-03-16

    摘要: According to one embodiment, a template substrate includes a substrate and a mask. The substrate includes a mesa region formed in a central portion of an upper surface of the substrate. The mesa region is configured to protrude more than a region of the substrate around the mesa region. An impurity is introduced into an upper layer portion of a partial region of a peripheral portion of the mesa region. The mask film is provided on the upper surface of the substrate.

    摘要翻译: 根据一个实施例,模板衬底包括衬底和掩模。 衬底包括形成在衬底的上表面的中心部分中的台面区域。 所述台面区域被构造为在所述台面区域周围突出多于所述基板的区域。 杂质被引入到台面区域的周边部分的部分区域的上层部分中。 掩模膜设置在基板的上表面上。

    Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product
    4.
    发明授权
    Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product 有权
    曝光掩模制造方法,绘图装置,半导体器件制造方法和掩模毛坯产品

    公开(公告)号:US08533634B2

    公开(公告)日:2013-09-10

    申请号:US12659396

    申请日:2010-03-08

    申请人: Masamitsu Itoh

    发明人: Masamitsu Itoh

    CPC分类号: G03F1/70

    摘要: A method of manufacturing an exposure mask includes generating or preparing flatness variation data relating to a mask blanks substrate to be processed into an exposure mask, the flatness variation data being data relating to change of flatness of the mask blank substrate caused when the mask blank substrate is chucked by a chuck unit of an exposure apparatus, generating position correction, data of a pattern to be drawn on the mask blanks substrate based on the flatness variation data such that a mask pattern of the exposure mask comes to a predetermined position in a state that the exposure mask is chucked by the chuck unit, and drawing a pattern on the mask blanks substrate, the drawing the pattern including drawing the pattern with correcting a drawing position of the pattern and inputting drawing data corresponding to the pattern and the position correction data into a drawing apparatus.

    摘要翻译: 制造曝光掩模的方法包括:生成或准备与待处理的掩模坯料基板相关的平坦度变化数据为曝光掩模,平坦度变化数据是与掩模坯料基板 由曝光装置的卡盘单元夹持,基于平坦度变化数据产生位置校正,要在掩模毛坯基板上绘制的图案的数据,使得曝光掩模的掩模图案在状态下到达预定位置 曝光掩模由卡盘单元卡住,并且在掩模坯料基板上绘制图案,绘制包括绘制图案的图案,校正图案的绘图位置并输入与图案相对应的绘图数据和位置校正数据 成为绘图装置。

    Pattern verification-test method, optical image intensity distribution acquisition method, and computer program
    6.
    发明授权
    Pattern verification-test method, optical image intensity distribution acquisition method, and computer program 有权
    模式验证测试方法,光学图像强度分布采集方法和计算机程序

    公开(公告)号:US08407629B2

    公开(公告)日:2013-03-26

    申请号:US13491639

    申请日:2012-06-08

    IPC分类号: G06F17/50

    CPC分类号: G03F1/86

    摘要: A pattern verification-test method according to an embodiment of the present invention includes: deriving an illumination condition at a verification-test subject position in a photomask surface of a mask pattern as a verification or a test subject based on the verification-test subject position and illumination condition information about a distribution of an illumination condition in a photomask surface of exposure light incident on the mask pattern, performing lithography simulation on the mask pattern based on the derived illumination condition and the mask pattern, and verifying or testing the mask pattern based on a result of the lithography simulation.

    摘要翻译: 根据本发明的实施例的图案验证测试方法包括:基于验证测试对象位置,在掩模图案的光掩模表面中的验证测试对象位置处作为验证或测试对象导出照明条件 以及关于入射到掩模图案的曝光光的光掩模表面中的照明条件的分布的照明条件信息,基于导出的照明条件和掩模图案对掩模图案进行光刻模拟,以及基于掩模图案的验证或测试 在光刻模拟的结果。

    Photomask manufacturing method and semiconductor device manufacturing method

    公开(公告)号:US08407628B2

    公开(公告)日:2013-03-26

    申请号:US12770062

    申请日:2010-04-29

    IPC分类号: G06F17/50 G03F1/00

    CPC分类号: G06F17/5081 G03F1/50

    摘要: This invention discloses a photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a mask pattern is formed on a transparent substrate, and measuring a mask in-plane distribution of the pattern dimensions. A transmittance correction coefficient map is generated by dividing a pattern formation region into a plurality of subregions, and determining a transmittance correction coefficient for each of the plurality of subregions. The transmittance correction value of each subregion is calculated on the basis of the pattern dimensional map and the transmittance correction coefficient map. The transmittance of the transparent substrate corresponding to each subregion is changed on the basis of the transmittance correction value.

    REFLECTIVE MASK, MANUFACTURING METHOD FOR REFLECTIVE MASK, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
    8.
    发明申请
    REFLECTIVE MASK, MANUFACTURING METHOD FOR REFLECTIVE MASK, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE 审中-公开
    反射掩模,反射掩模的制造方法和半导体器件的制造方法

    公开(公告)号:US20120040293A1

    公开(公告)日:2012-02-16

    申请号:US13282497

    申请日:2011-10-27

    IPC分类号: G03F7/20 B82Y40/00

    CPC分类号: G03F1/24

    摘要: A reflective mask comprising: a reflective layer that is arranged on a surface on a side on which EUV light is irradiated and reflects the EUV light; a buffer layer containing Cr that is arranged on a side of the reflective layer on which the EUV light is irradiated and covers an entire surface of the reflective layer; and a non-reflective layer that is arranged on a side of the buffer layer on which the EUV light is irradiated and in which an absorber that absorbs the irradiated EUV light is arranged in a position corresponding to a mask pattern to be reduced and transferred onto a wafer.

    摘要翻译: 一种反射掩模,包括:反射层,其被布置在其上照射有EUV光的一侧的表面上并且反射所述EUV光; 包含Cr的缓冲层,其布置在其上照射有EUV光的反射层的一侧并覆盖反射层的整个表面; 以及布置在其上照射有EUV光的缓冲层侧的非反射层,并且其中吸收被照射的EUV光的吸收体被布置在与要被还原并转移到其上的掩模图案相对应的位置 晶圆。

    Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product
    9.
    发明申请
    Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product 有权
    曝光掩模制造方法,绘图装置,半导体器件制造方法和掩模毛坯产品

    公开(公告)号:US20100228379A1

    公开(公告)日:2010-09-09

    申请号:US12659396

    申请日:2010-03-08

    申请人: Masamitsu Itoh

    发明人: Masamitsu Itoh

    IPC分类号: G06F19/00

    CPC分类号: G03F1/70

    摘要: A method of manufacturing an exposure mask includes generating or preparing flatness variation data relating to a mask blanks substrate to be processed into an exposure mask, the flatness variation data being data relating to change of flatness of the mask blank substrate caused when the mask blank substrate is chucked by a chuck unit of an exposure apparatus, generating position correction, data of a pattern to be drawn on the mask blanks substrate based on the flatness variation data such that a mask pattern of the exposure mask comes to a predetermined position in a state that the exposure mask is chucked by the chuck unit, and drawing a pattern on the mask blanks substrate, the drawing the pattern including drawing the pattern with correcting a drawing position of the pattern and inputting drawing data corresponding to the pattern and the position correction data into a drawing apparatus.

    摘要翻译: 制造曝光掩模的方法包括:生成或准备与待处理的掩模坯料基板相关的平坦度变化数据为曝光掩模,平坦度变化数据是与掩模坯料基板 由曝光装置的卡盘单元夹持,基于平坦度变化数据产生位置校正,要在掩模毛坯基板上绘制的图案的数据,使得曝光掩模的掩模图案在状态下到达预定位置 曝光掩模由卡盘单元卡住,并且在掩模坯料基板上绘制图案,绘制包括绘制图案的图案,校正图案的绘图位置并输入与图案相对应的绘图数据和位置校正数据 成为绘图装置。

    Method for selecting photomask substrate, method for manufacturing photomask, and method for manufacturing semiconductor device
    10.
    发明授权
    Method for selecting photomask substrate, method for manufacturing photomask, and method for manufacturing semiconductor device 失效
    光掩模基板的选择方法,光掩模的制造方法以及半导体装置的制造方法

    公开(公告)号:US07740994B2

    公开(公告)日:2010-06-22

    申请号:US11585130

    申请日:2006-10-24

    IPC分类号: G03F1/00

    CPC分类号: G03F1/84 G03F1/44

    摘要: According to an aspect of the invention, there is provided a method for selecting a photomask substrate, including dividing a chip area scheduled to be arranged on the photomask substrate regarding a specific transfer pattern layer into a management pattern area in which an element pattern changed in shape by birefringence of the photomask substrate is arranged, and an area other than the management pattern area, setting a standard value of a size of birefringence of an area in which the management pattern area of the photomask substrate is arranged, inspecting the size of the birefringence of each of a plurality of photomask substrate candidates, and selecting a photomask substrate, in which the size of the birefringence satisfies the standard value, as a photomask substrate of the specific transfer pattern layer from the plurality of photomask substrate candidates.

    摘要翻译: 根据本发明的一个方面,提供了一种用于选择光掩模衬底的方法,包括将针对特定传输图案层布置在光掩模衬底上的芯片区域划分成其中元件图案改变的管理图案区域 布置光掩模基板的双折射形状,并且设置管理图案区域以外的区域,设置布置有光掩模基板的管理图案区域的区域的双折射尺寸的标准值,检查 多个光掩模衬底候选中的每一个的双折射,并且从多个光掩模衬底候选中选择其中双折射的尺寸满足标准值的光掩模衬底作为特定转移图案层的光掩模衬底。