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1.发明授权
公开(公告)号：US5594436A
公开(公告)日：1997-01-14
申请号：US327062
申请日：1994-10-21
CPC分类号： G11B20/10 , G11B20/1426
摘要： An apparatus and method for detecting analog signals representing patterns of n-bit RLL-encoded data read from a data storage device. R integrators each integrate the analog signal over successive time periods consisting of a preselected number n of bit cycles, where n>1, weighted by a preselected set of n orthogonal signals that are staircase functions which vary each bit cycle to provide R integrated weighted outputs. The R integrated weighted outputs are converted by a lookup table or read-only memory into an n-bit digital representation corresponding to a unique one of the n-bit analog data patterns.
摘要翻译： 一种用于检测表示从数据存储装置读取的n位RLL编码数据的模式的模拟信号的装置和方法。 R个积分器每个在连续的时间段上对模拟信号进行积分，该连续的时间段由一个预选的n个位循环组成，其中n≥1，由n个正交信号的预选集合加权，n个正交信号是阶梯函数，它们改变每个位周期以提供R个积分加权输出 。 R集成加权输出由查找表或只读存储器转换成对应于n位模拟数据模式中的唯一一个的n位数字表示。
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2.发明授权Combination parallel/serial execution of sequential algorithm for data compression/decompression 失效组合并行/串行执行数据压缩/解压缩的顺序算法
公开(公告)号：US5384567A
公开(公告)日：1995-01-24
申请号：US89211
申请日：1993-07-08
CPC分类号： H03M7/3086 , G06T9/005
摘要： An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer compresses an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
摘要翻译： 一种用于执行顺序数据压缩算法的装置和方法，其特别适用于在设备（与主机不同）控制器中需要数据压缩的地方。 历史缓冲区压缩i个相同水平切片单元的阵列。 每个片单元存储j个符号以定义其中每个片单元中的符号被精确地i个符号分隔的j个分离块。 i个输入符号的串中的符号被i个比较器与先前存储在片单元中的符号并行地进行比较，以识别符号的匹配序列。 控制单元控制顺序算法的执行，以使比较器平行扫描符号，但在每个块中顺序扫描符号，并使符号的匹配序列和非匹配序列存储在阵列中。 选择参数i和j以限制在基于算法执行速度与硬件成本的折衷来执行算法时实现期望的效率程度所需的比较器的数量。 优先编码器根据由片单元输出的信号计算每个j，i地址，其中标识匹配序列，但是它输出这些地址中只有一个（例如最小的）的地址。
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3.发明授权Location dependent variable error correction processing for multi-track recording media using variable length coding means 失效使用可变长度编码装置的多轨记录介质的位置相关变量纠错处理
公开(公告)号：US5487077A
公开(公告)日：1996-01-23
申请号：US247446
申请日：1994-05-23
CPC分类号： H03M13/35 , G11B20/1833 , G11B20/1258
摘要： The error correction code capability of the linear recording density of a zone of contiguous recording tracks on a surface or volume having at lest two zones of different average linear recording density is adjusted. Each zone has associated therewith a parameter pair (r,R) defining the number of error correction bytes r to be appended to data blocks to form a codeword written to tracks within the zone and the number R.ltoreq.(r/2-1) of correctable errors in the event of a non-zero remainder detected upon readback of a codeword from a track within the zone. The r parameter controls the length of a shift register type encoder syndrome generator.
摘要翻译： 在具有不同平均线性记录密度的两个区域的表面或体积上的连续记录轨迹区域的线性记录密度的纠错码能力被调整。 每个区域具有与其相关联的参数对（r，R），其定义要附加到数据块的纠错字节数r，以形成写入该区域内的轨道的码字，并且数量R（r / 2-1 ）在从区域内的轨道读取码字时检测到非零余数的情况下的可校正错误。 r参数控制移位寄存器型编码器校正发生器的长度。
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4.发明授权Adjustable error-correction composite Reed-Solomon encoder/syndrome generator 失效可纠正的纠错复合Reed-Solomon编码器/综合发生器
公开(公告)号：US5444719A
公开(公告)日：1995-08-22
申请号：US8922
申请日：1993-01-26
CPC分类号： G11B20/1833 , H03M13/151 , H03M13/35
摘要： A composite encoder/syndrome generating circuit computes both check symbols and error syndromes using a single set of multiplier devices with varying tap weights having values that provide a maximum preselected error correction capability but is readily adjustable, such as by programmable latches, to eliminate from the circuit selectable multiplier devices to reduce the error correction capability without requiring a change in the tap weight values. The circuit may be used to increase or decrease error correction capability (a) according to which of a plurality of concentric bands of recording tracks is being accessed in a banded direct access data storage device, (b) according to noise level as sensed in a data communications channel having an output subject to noise, or (c) according to changes in sending rates in a sending device that sends data at variable rates.
摘要翻译： 复合编码器/校正子产生电路使用具有变化的抽头权重的单组乘法器装置来计算校验符号和误差校正子，所述抽头权重具有提供最大预选误差校正能力但容易调节的值，例如通过可编程锁存器，以从 电路选择乘法器设备，以减少纠错能力，而不需要抽头重量值的变化。 电路可以用于增加或减少纠错能力（a），根据在带状直接存取数据存储装置中正在访问多个记录磁道的同心磁带中的哪一个，（b）根据在 数据通信信道具有受噪声的输出，或（c）根据以可变速率发送数据的发送设备的发送速率的变化。
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公开(公告)号：US5638065A
公开(公告)日：1997-06-10
申请号：US489863
申请日：1995-06-13
CPC分类号： G11B20/1426 , G11B20/10009
摘要： Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.
摘要翻译： RLL编码信道中的模拟信号的并行ML处理，其中（1）信道的当前状态的向量和信道的下一状态的矢量使用模拟信号的沃尔什变换矢量系数来计算; （2）当前状态矢量和下一状态向量以及在模拟匹配滤波器中预先计算的矢量值用于产生与预选阈值进行比较的矢量标量积，用于产生在数字顺序有限状态机中使用的二进制判决输出以产生ML 符号决定 （3）ML符号决定被反馈并用于从下一状态的向量中减去当前状态向量的符号间干扰值，以将下一状态向量变换为更新的当前状态向量。
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公开(公告)号：US4949196A
公开(公告)日：1990-08-14
申请号：US175171
申请日：1988-03-30
摘要： This disclosure concerns for generating asymmetrically constrained run-length-limited encoded data from a serialized binary string of 1's and 0's. The method comprises the steps of encoding the input data bits using a run-length-limited constraint in the form of M/N (d,k), where M is the number of input data bits, N is the number of output bits associated therewith, d is the minimum number of 0 data bits between adjacent data bit 1's, and k is the maximum number of 0 data bits between adjacent 1's; and alternating the values of d and k between a set (d.sub.1, k.sub.1) and a set (d.sub.2, k.sub.2), respectively, where d.sub.1 .noteq.d.sub.2. The apparatus comprises means for generating N output data bits in response to M input data bits and for generating data bit 0's between data bit 1's based upon a run-length-limited coding constraints (d.sub.1, k.sub.1) and (d.sub.2, k.sub.2), where constraints (d.sub.1, k.sub.1) and (d.sub.2, k.sub.2) apply alternately to runs of zeroes between output data ones. Fractional numerical values of d.sub.1 and d.sub.2 can be employed in the method or apparatus.
摘要翻译： 本公开涉及从1和0的串行化二进制串生成不对称约束的游程长度限制编码数据。 该方法包括以M / N（d，k）形式的游程限制约束对输入数据比特进行编码的步骤，其中M是输入数据比特数，N是相关联的输出比特数 因此，d是相邻数据位1之间的0个数据位的最小数量，k是相邻1之间的0个数据位的最大数量; 并且分别在集合（d1，k1）和集合（d2，k2）之间交替d和k的值，其中d1 NOTEQUAL d2。 该装置包括用于响应于M个输入数据位产生N个输出数据位并用于基于游程长度限制编码约束（d1，k1）和（d2，k2）在数据位1之间产生数据位0的装置，其中 约束（d1，k1）和（d2，k2）交替应用于输出数据之间的零运行。 d1和d2的分数值可以在该方法或装置中使用。
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公开(公告)号：US4882583A
公开(公告)日：1989-11-21
申请号：US200322
申请日：1988-05-31
CPC分类号： H03M5/145
摘要： Uncompressed data is represented in a constrained code for transmission through a channel which may include record media. A d,k code having a code rate of m/n is employed. "d" represents the minimum number of successive zeros in the channel code while k represents the maximum number of zeros in the channel code. "n" is an integer representing the number of code bits in a channel group. The encoding and decoding follows a sliding block coding and decoding algorithm. In the channel coding, the number of successive ones is limited to being not less than two, in some coding it can be a value of d-1. The modification of the d,k code results in decreasing error propagation while increasing the recorded information density. This increase is achieved by increasing the channel code dictionary.
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公开(公告)号：US4951284A
公开(公告)日：1990-08-21
申请号：US284979
申请日：1988-12-14
CPC分类号： H03M13/159 , G11B20/1833 , H03M13/1515 , H03M13/29 , H03M13/2903 , H03M13/2906 , H03M13/293
摘要： A method and means is described for correcting multiple error bursts in data recorded on a storage medium in blocks, comprising a plurality of subblocks. After reading the data, decoded block check syndromes are algebraically summed with estimated block check syndromes to provide a set of syndromes for a code for locating subblocks having an error burst. This set of syndromes is decoded to identify each subblock having an error burst. Concurrently block level syndromes are computer to identify the locations and values of errors within the subblocks having error bursts. During writing, the data in all subblocks of a block is encoded and block level syndromes are generated for these subblocks. These block level syndromes are multiplied by a series of preselected weighting factors (.alpha..sup.1 . . ..alpha..sup.1(B-1)) according to the location index 1 of the sublock within the block and as multiplied, each is stored in a different one of B buffers. These are cumulatively summed to produce block check syndromes, which are encoded after the last subblock of the block is written to provide check bytes for their protection. These check bytes and the weight cumulative sums are stored on the medium at the end of the block as block check syndromes.
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公开(公告)号：US4994995A
公开(公告)日：1991-02-19
申请号：US493568
申请日：1990-03-14
摘要： A bit-serial division method for computing the value v/u, where v and u are each n-bit vectors that are elements in a finite Galois field GF(2.sup.n) consisting of 2.sup.n elements. The n-bit components of each element in the field are coordinates of the element in a canonical basis of the field. Vector u is converted from canonical basis to a dual basis. Vector u in dual basis also comprises n bits in the finite field ordered according to an index i that takes on values from 0 to (n-1). All bits n of the converted vector u are loaded into a shift register in parallel, then converted from dual basis back to canonical basis to produce a single bit output w.sub.0 from a lookup table which generates bitwise the inverse of the n-bit vector u. The bits in the shift register are shifted (n-1) times to generate successive additional single bit outputs w.sub.i with said lookup table. Then each bit w.sub.i is multiplied by the vector v and a corresponding element c.sub.i in dual basis to generate a cumulative sum of these products that provides, upon completion of the (n-1) shifts, the bit-serial division result v/u.
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