公开(公告)号：US20140122900A1

公开(公告)日：2014-05-01

申请号：US14058106

申请日：2013-10-18

申请人： Infosys Limited

发明人： Kulvaibhav Kaushik ,  Vijayaraghavan Varadharajan ,  Rajarathnam Nallusamy

IPC分类号： G06F21/60 ,  G06F17/30

CPC分类号： G06F21/6227 ,  G06F7/725 ,  G06F7/726 ,  G06F17/30109 ,  G06F17/30424 ,  G06F2221/2107 ,  H04L9/3013 ,  H04L63/0428 ,  H04L63/1441 ,  H04L67/1097

摘要： The present invention relates to a computer-implemented method, system and computer readable medium for providing a searching over encrypted keywords in a database. The method comprises the steps of generating at least one keyword, generating a plurality of different encrypted keywords corresponding to said keyword, storing said at least one encrypted keyword in said database; generating a plurality of different trapdoors for said keyword, verifying said plurality of different trapdoors with said plurality of different encrypted keywords corresponding to said keyword and determining said keyword if said plurality of different trapdoors match with one said encrypted keyword corresponding to said keyword else determining said keyword is not found.

摘要翻译： 本发明涉及一种计算机实现的方法，系统和计算机可读介质，用于在数据库中提供对加密关键字的搜索。 该方法包括以下步骤：生成至少一个关键字，产生与所述关键字对应的多个不同的加密关键字，将所述至少一个加密的关键字存储在所述数据库中; 为所述关键字生成多个不同的陷门，用与所述关键词相对应的所述多个不同加密关键字验证所述多个不同的陷阱，并且如果所述多个不同的陷阱与所述关键字对应的所述多个不同的陷阱与所述关键字相匹配，则确定所述关键字，否则确定所述 关键字未找到。

公开(公告)号：US08375077B2

公开(公告)日：2013-02-12

申请号：US12239927

申请日：2008-09-29

申请人： Pierre Laurent

发明人： Pierre Laurent

IPC分类号： G06F7/00

CPC分类号： G06F7/726

摘要： Methods, apparatus and media for performing polynomial arithmetic operations over a Galois field having characteristic 2 and size 1 are disclosed. Such methods, apparatus and media include generating a binary representation of a polynomial over a Galois field having characteristic 2 and size 1, generating a plurality of right shifted binary representations of the first polynomial, and generating a binary representation of the polynomial reciprocal based upon a bitwise exclusive-OR of the binary representation of the polynomial and one or more right shifted binary representations selected from the plurality of right shifted binary representations.

摘要翻译： 公开了在具有特征2和尺寸1的伽罗瓦域上执行多项式算术运算的方法，装置和介质。 这样的方法，装置和媒体包括在具有特征2和尺寸1的伽罗瓦域上生成多项式的二进制表示，产生第一多项式的多个右移二进制表示，并且基于一个多项式互逆生成多项式互逆的二进制表示 多项式的二进制表示和从多个右移二进制表示中选择的一个或多个右移二进制表示的按位异或。

公开(公告)号：US20130007086A1

公开(公告)日：2013-01-03

申请号：US13615795

申请日：2012-09-14

申请人： Rene Caupolican Peralta ,  Joan Boyar

发明人： Rene Caupolican Peralta ,  Joan Boyar

IPC分类号： G06F7/50 ,  H03K19/21

CPC分类号： G06F7/726 ,  H04L9/0631 ,  H04L2209/08 ,  H04L2209/122

摘要： A method of simplifying a combinational circuit establishes an initial combinational circuit operable to calculate a set of target signals. A quantity of multiplication operations performed in a first portion of the initial combinational circuit is reduced to create a first, simplified combinational circuit. The first portion includes only multiplication operations and addition operations. A quantity of addition operations performed in a second portion of the first, simplified combinational circuit is reduced to create a second, simplified combinational circuit. The second portion includes only addition operations. Also, the second, simplified combinational circuit is operable to calculate the target signals using fewer operations than the initial combinational circuit.

摘要翻译： 简化组合电路的方法建立了可操作以计算一组目标信号的初始组合电路。 在初始组合电路的第一部分中执行的乘法运算量被减少以产生第一简化的组合电路。 第一部分仅包括乘法运算和加法运算。 在第一简化组合电路的第二部分中执行的加法运算量被减少以产生第二简化组合电路。 第二部分仅包括附加操作。 此外，第二简化组合电路可操作以使用比初始组合电路更少的操作来计算目标信号。

公开(公告)号：US08243919B2

公开(公告)日：2012-08-14

申请号：US12039996

申请日：2008-02-29

申请人： Nevine Maurice Nassif Ebeid

发明人： Nevine Maurice Nassif Ebeid

IPC分类号： H04K1/00

CPC分类号： G06F7/725 ,  G06F7/726 ,  G06F2207/7242 ,  H04L9/003 ,  H04L9/3066 ,  H04L2209/80 ,  H04W12/12

摘要： When multiplicative splitting is used to hide a scalar in an Elliptic Curve scalar Multiplication ECSM operation, the associated modular division operation employs the known Almost Montgomery Inversion algorithm. By including dummy operations in some of the branches of the main iteration loop of the Almost Montgomery Inversion algorithm, all branches of the algorithm may be viewed, from the perspective of a Power Analysis-based attack, as equivalent and, accordingly, devoid of information useful in determining the value of the scalar, which may be a cryptographic private key.

摘要翻译： 当乘法分割用于隐藏椭圆曲线乘法ECSM操作中的标量时，相关联的模块划分操作采用已知的几乎蒙哥马利反演算法。 通过在几乎蒙哥马利反转算法的主迭代循环的一些分支中包括虚拟操作，从基于功率分析的攻击的角度来看，该算法的所有分支可以等效，因此没有信息 可用于确定标量的值，其可以是密码私钥。

公开(公告)号：US20110295921A1

公开(公告)日：2011-12-01

申请号：US12790645

申请日：2010-05-28

申请人： Xu Yang ,  Xiaolin Quan ,  Dongmei Zhang

发明人： Xu Yang ,  Xiaolin Quan ,  Dongmei Zhang

IPC分类号： G06F7/535

CPC分类号： G06F7/724 ,  G06F7/726

摘要： A hybrid greatest common divisor (GCD) calculator analyzes characteristics of polynomials and selects a particular GCD algorithm from multiple available GCD algorithms based on a combination of characteristics of the polynomials. The selected GCD algorithm is then applied to calculate the GCD of the polynomials.

摘要翻译： 混合最大公约数（GCD）计算器分析多项式的特征，并且基于多项式的特征的组合从多个可用的GCD算法中选择特定的GCD算法。 然后应用所选择的GCD算法来计算多项式的GCD。

公开(公告)号：US20100322412A1

公开(公告)日：2010-12-23

申请号：US12820148

申请日：2010-06-22

申请人： Chia-Yu Hung ,  Tsung-Li Yeh

发明人： Chia-Yu Hung ,  Tsung-Li Yeh

IPC分类号： H04L9/28 ,  G06F7/00

CPC分类号： G06F7/726 ,  H04L9/0631 ,  H04L2209/122

摘要： A method for dealing with Galois Field computation includes: providing an operating circuit which has at least a multiplicative inverse unit; and using the multiplicative inverse unit to execute at least a plurality of isomorphism maps for deriving a multiplicative inverse at a specific Galois Field corresponding to an input data, wherein the plurality of isomorphism maps include at least a change of basis.

摘要翻译： 用于处理伽罗瓦域计算的方法包括：提供至少具有乘法逆单位的操作电路; 以及使用所述乘法逆单元执行至少多个同构映射，以在对应于输入数据的特定伽罗瓦域导出乘法逆，其中所述多个同构映射至少包括基础变化。

公开(公告)号：US07089276B2

公开(公告)日：2006-08-08

申请号：US10273002

申请日：2002-10-18

申请人： David H. Miller ,  Richard W. Koralek

发明人： David H. Miller ,  Richard W. Koralek

IPC分类号： G06F7/00

CPC分类号： G06F7/726 ,  G06F2207/3884

摘要： A modular Galois-field subfield-power integrated inverter-multiplier circuit that may be used to perform Galois-field division over GF(245). The integrated inverter-multiplier circuit combines subfield-power and parallel multiplication and inversion operations performed therein. The circuit is modular, has a relatively low gate count, and is easily pipelined because it does not use random logic. The circuit implements mathematical calculations known as “Galois-field arithmetic” that are required for a variety of digital signaling and processing applications such as Reed-Solomon and Bose-Chaudhuri-Hochquenghem (BCH) error-correction coding systems. Galois-field division is particularly difficult, typically requiring either a great deal of time or highly complex circuits, or both. The circuit uses a unique combination of subfield and power inversion techniques to carry out multiplicative inversion. Furthermore, the circuit uniquely implements Galois-field division by carrying out the multiplicative inversion and the multiplication simultaneously and in parallel. This substantially increases computation speed. The modularity and pipelineability of the present invention also make system design easier and increases the speed and reduces the gate count of an integrated circuit embodying the inverter-multiplier circuit.

摘要翻译： 可以用于在GF（245）上执行Galois-field分割的模块化Galois-field子场功率集成反相器乘法器电路。 集成逆变器倍增器电路组合了其中执行的子场功率和并行乘法和反相操作。 电路是模块化的，具有相对较低的门数，并且由于不使用随机逻辑而容易流水线化。 该电路实现了诸如Reed-Solomon和Bose-Chaudhuri-Hochquenghem（BCH）纠错编码系统的各种数字信令和处理应用所需的称为“伽罗瓦域算术”的数学计算。 伽罗瓦域划分是特别困难的，通常需要大量的时间或高度复杂的电路，或两者兼有。 该电路使用子场和功率反演技术的独特组合来执行乘法反演。 此外，电路通过同时并行并行执行乘法反演和乘法来唯一地实现伽罗瓦域划分。 这大大增加了计算速度。 本发明的模块化和可流水性还使系统设计更容易，并且提高速度并降低体现逆变器倍增器电路的集成电路的门数。

公开(公告)号：US20060126828A1

公开(公告)日：2006-06-15

申请号：US11021351

申请日：2004-12-23

申请人： Joong-chul Yoon ,  Sung-woo Lee

发明人： Joong-chul Yoon ,  Sung-woo Lee

IPC分类号： H04L9/28

CPC分类号： G06F7/726 ,  G06F7/728 ,  G06F2207/7223

摘要： In an inverse calculation circuit, an inverse calculation method, and a storage medium encoded with a computer readable computer program code, a random number generator generates a first random number and a second random number; and an inverter receives a plurality of first bits expressing a first element of a finite field(s) as first inputs, receives a plurality of second bits expressing a second element of a finite field(s) as second inputs. In response to the first and second random numbers, the inverter outputs a plurality of third bits expressing the inverse elements of the first element. The first random number prevents a different power analysis (DPA) decryption attack, and the second random number prevents a timing decryption attack.

摘要翻译： 在逆计算电路中，逆计算方法和用计算机可读计算机程序代码编码的存储介质，随机数生成器生成第一随机数和第二随机数; 并且逆变器接收表示有限域的第一元素的多个第一比特作为第一输入，接收表示有限域的第二元素的多个第二比特作为第二输入。 响应于第一和第二随机数，逆变器输出表示第一元素的反向元素的多个第三比特。 第一个随机数防止了不同的功率分析（DPA）解密攻击，第二个随机数阻止了定时解密攻击。

公开(公告)号：US20040158598A1

公开(公告)日：2004-08-12

申请号：US10771592

申请日：2004-02-03

发明人： Chun Pyo Hong ,  ChangHoon Kim

IPC分类号： G06F007/32 ,  G06F015/00 ,  G06F007/00

CPC分类号： G06F7/724 ,  G06F7/726

摘要： Disclosed herein is an arithmetic logic unit over a finite field GF(2m). Arithmetic logic units consistent with the present invention are disclosed as implemented using a division algorithm based on a binary greatest common divisor algorithm and a Most Significant Bit-first multiplication algorithm. The arithmetic logic unit can perform both a multiplication and a division using shared logic. Since the arithmetic logic unit has no limitations in the selection of an irreducible polynomial, and it is very regular and easily formed as a module, the arithmetic logic unit of the present invention has high expansibility and flexibility with respect to the size m of a field. Further, since the arithmetic logic unit of the present invention can perform a multiplication and a division using shared logic, it is very suitable to implement an encryption system for application products requiring a small size, such as smart cards or wireless communication devices.

摘要翻译： 这里公开的是在有限域GF（2m）上的算术逻辑单元。 公开了使用基于二进制最大公因数算法和最高有效位优先乘法算法的分割算法实现的与本发明一致的算术逻辑单元。 算术逻辑单元可以使用共享逻辑执行乘法和除法。 由于算术逻辑单元在不可约多项式的选择中没有限制，并且它非常规则且容易地形成为模块，所以本发明的算术逻辑单元相对于场的尺寸m具有高的可扩展性和灵活性 。 此外，由于本发明的算术逻辑单元可以使用共享逻辑执行乘法和除法，所以对于需要小尺寸的应用产品（例如智能卡或无线通信设备）实施加密系统是非常合适的。

公开(公告)号：US20040078408A1

公开(公告)日：2004-04-22

申请号：US10273002

申请日：2002-10-18

发明人： David H. Miller ,  Richard W. Koralek

IPC分类号： G06F007/00

CPC分类号： G06F7/726 ,  G06F2207/3884

摘要： A modular Galois-field subfield-power integrated inverter-multiplier circuit that may be used to perform Galois-field division over GF(245). The integrated inverter-multiplier circuit combines subfield-power and parallel multiplication and inversion operations performed therein. The circuit is modular, has a relatively low gate count, and is easily pipelined because it does not use random logic. The circuit implements mathematical calculations known as nullGalois-field arithmeticnull that are required for a variety of digital signaling and processing applications such as Reed-Solomon and BCH error-correction coding systems. Galois-field division is particularly difficult, typically requiring either a great deal of time or highly complex circuits, or both. The circuit uses a unique combination of subfield and power inversion techniques to carry out multiplicative inversion. Furthermore, the circuit uniquely implements Galois-field division by carrying out the multiplicative inversion and the multiplication simultaneously and in parallel. This substantially increases computation speed. The modularity and pipelineability of the present invention also make system design easier and increases the speed and reduces the gate count of an integrated circuit embodying the inverter-multiplier circuit.

摘要翻译： 可以用于在GF（245）上执行Galois-field分割的模块化Galois-field子场功率集成反相器乘法器电路。 集成逆变器倍增器电路组合了其中执行的子场功率和并行乘法和反相操作。 电路是模块化的，具有相对较低的门数，并且由于不使用随机逻辑而容易流水线化。 该电路实现了诸如Reed-Solomon和BCH纠错编码系统之类的各种数字信令和处理应用所需的称为“伽罗瓦域算术”的数学计算。 伽罗瓦域划分是特别困难的，通常需要大量的时间或高度复杂的电路，或两者兼有。 该电路使用子场和功率反演技术的独特组合来执行乘法反演。 此外，电路通过同时并行并行执行乘法反演和乘法来唯一地实现伽罗瓦域划分。 这大大增加了计算速度。 本发明的模块化和可流水性还使系统设计更容易，并且提高速度并降低体现逆变器倍增器电路的集成电路的门数。