公开(公告)号：US20110153046A1

公开(公告)日：2011-06-23

申请号：US12926946

申请日：2010-12-20

申请人： Makoto Nagasue ,  Naotaka Saito

发明人： Makoto Nagasue ,  Naotaka Saito

IPC分类号： G06F17/00

CPC分类号： H03G3/3005 ,  H03G3/001 ,  H03G3/3089

摘要： A signal processing device includes a first amplifier, a converter, a signal processor, a controller, and a second amplifier. The first amplifier amplifies a level of an externally input analog audio signal with a first gain whose value is variable. The converter converts the analog audio signal amplified by the first amplifier into a digital audio signal. The signal processor that performs tone control signal processing on the digital audio signal. The controller detects a level of the digital audio signal before the signal processing and controls the value of the first gain in accordance with the detected level. The second amplifier detects a level of the digital audio signal after the signal processing and amplifies the digital audio signal after the signal processing with a second gain determined in accordance with the detected level and the first gain whose value has been controlled by the controller.

摘要翻译： 信号处理装置包括第一放大器，转换器，信号处理器，控制器和第二放大器。 第一个放大器放大外部输入的模拟音频信号的电平，其中第一个增益的值是可变的。 转换器将由第一放大器放大的模拟音频信号转换为数字音频信号。 对数字音频信号执行音调控制信号处理的信号处理器。 控制器在信号处理之前检测数字音频信号的电平，并根据检测到的电平来控制第一增益的值。 第二放大器在信号处理后检测数字音频信号的电平，并且在信号处理之后放大数字音频信号，其中第二增益是根据检测到的电平确定的，而第一增益的值已由控制器控制。

公开(公告)号：US20110150237A1

公开(公告)日：2011-06-23

申请号：US12926947

申请日：2010-12-20

申请人： Makoto Nagasue ,  Naotaka Saito

发明人： Makoto Nagasue ,  Naotaka Saito

IPC分类号： H04B15/00 ,  H03G3/00 ,  H03F99/00

CPC分类号： H03G3/001 ,  H03F3/187 ,  H03F3/45475 ,  H03F2203/45138 ,  H03F2203/45522 ,  H03F2203/45528 ,  H03G3/301 ,  H03G3/3026 ,  H03M3/486 ,  H03M3/49

摘要： A signal processing device includes a non-inverting amplifier, an inverting amplifier, a converter, and a controller. The non-inverting amplifier amplifies a level of an analog sound signal input from outside with a first gain whose value is variable. The inverting amplifier amplifies a level of the analog sound signal amplified by the non-inverting amplifier with a second gain whose value is variable. The converter converts the analog sound signal amplified by the inverting amplifier to a digital sound signal. The controller detects a level of the digital sound signal converted by the converter and, in accordance with the detected level of the digital sound signal converted by the converter, controls the first gain and the second gain such that a level of the analog sound signal input to the converter is at a pre-specified level.

摘要翻译： 信号处理装置包括非反相放大器，反相放大器，转换器和控制器。 非反相放大器利用其值可变的第一增益来放大从外部输入的模拟声音信号的电平。 反相放大器放大由非反相放大器放大的模拟声音信号的电平，其值可变的第二增益。 转换器将由反相放大器放大的模拟声音信号转换为数字声音信号。 控制器检测由转换器转换的数字声音信号的电平，并且根据由转换器转换的数字声音信号的检测电平来控制第一增益和第二增益，使得模拟声音信号输入的电平 到转换器处于预定级别。

公开(公告)号：US09071216B2

公开(公告)日：2015-06-30

申请号：US12926946

申请日：2010-12-20

申请人： Makoto Nagasue ,  Naotaka Saito

发明人： Makoto Nagasue ,  Naotaka Saito

IPC分类号： G06F17/00 ,  H03G3/30 ,  H03G3/00 ,  H04R3/00

CPC分类号： H03G3/3005 ,  H03G3/001 ,  H03G3/3089

摘要： A signal processing device includes a first amplifier, a converter, a signal processor, a controller, and a second amplifier. The first amplifier amplifies a level of an externally input analog audio signal with a first gain whose value is variable. The converter converts the analog audio signal amplified by the first amplifier into a digital audio signal. The signal processor that performs tone control signal processing on the digital audio signal. The controller detects a level of the digital audio signal before the signal processing and controls the value of the first gain in accordance with the detected level. The second amplifier detects a level of the digital audio signal after the signal processing and amplifies the digital audio signal after the signal processing with a second gain determined in accordance with the detected level and the first gain whose value has been controlled by the controller.

摘要翻译： 信号处理装置包括第一放大器，转换器，信号处理器，控制器和第二放大器。 第一个放大器放大外部输入的模拟音频信号的电平，其中第一个增益的值是可变的。 转换器将由第一放大器放大的模拟音频信号转换为数字音频信号。 对数字音频信号执行音调控制信号处理的信号处理器。 控制器在信号处理之前检测数字音频信号的电平，并根据检测到的电平来控制第一增益的值。 第二放大器在信号处理后检测数字音频信号的电平，并且在信号处理之后放大数字音频信号，其中第二增益是根据检测到的电平确定的，第一增益的值已由控制器控制。

公开(公告)号：US20070131093A1

公开(公告)日：2007-06-14

申请号：US11517335

申请日：2006-09-08

申请人： Makoto Nagasue

发明人： Makoto Nagasue

IPC分类号： G10H7/00

CPC分类号： G10H7/002 ,  G10H2230/041

摘要： A sound system includes, separately, a first clock generation section that generates a system clock for supply to a CPU or others via an internal bus, and a second clock generation section that generates a waveform synthesis clock for supply to a waveform synthesizer of a sound accelerator. The first clock generation section is so configured as to output a frequency corresponding to a value set by the CPU to a frequency setting register. Note here that the frequency of the second clock generation section may be set variable by the CPU. This enables operation with a further-optimum clock frequency so that the increase of power consumption caused by unnecessarily high-speed clock signals can be prevented in the sound system.

摘要翻译： 声音系统分别包括产生用于经由内部总线向CPU等提供的系统时钟的第一时钟生成部，以及生成用于提供给声音的波形合成器的波形合成时钟的第二时钟生成部 加速器。 第一时钟生成部分被配置为将与CPU设置的值相对应的频率输出到频率设置寄存器。 这里注意，第二时钟生成部的频率可以由CPU设定为可变。 这使得能够以更优化的时钟频率进行操作，从而可以在声音系统中防止由不必要的高速时钟信号引起的功率消耗的增加。

公开(公告)号：US06687155B2

公开(公告)日：2004-02-03

申请号：US10434217

申请日：2003-05-09

申请人： Makoto Nagasue

发明人： Makoto Nagasue

IPC分类号： G11C1612

CPC分类号： G11C27/005

摘要： An analog storage flash memory by which sufficient write accuracy can be obtained even when the write speed of the memory cell transistor disperses due to manufacturing dispersion or other reasons. A read voltage adjustment circuit outputs the read voltage generated by a read voltage generation circuit as is, or drops and outputs the read voltage. A write voltage adjustment circuit outputs the write voltage generated by a write voltage generation circuit as is, or drops and outputs the write voltage. A write control circuit repeats the write operation at the write voltage Vw until the memory cell transistor turns OFF at the read voltage Vr−&Dgr;Vr in the first write cycle, and repeats the write operation at the write voltage Vw−&Dgr;Vw until the memory transistor turns OFF at the read voltage Vr in the second write cycle.

摘要翻译： 即使当存储单元晶体管的写入速度由于制造分散或其他原因而分散时，也能够获得足够的写入精度的模拟存储闪存。 读取电压调整电路按原样输出由读取电压产生电路产生的读取电压，或者降低并输出读取的电压。 写入电压调整电路输出由写入电压产生电路产生的写入电压，或者降低并输出写入电压。 写入控制电路以写入电压Vw重复写入操作，直到存储单元晶体管在第一写入周期中的读取电压Vr-ΔVr处截止，并以写入电压Vw-DeltaVw重复写入操作，直到存储晶体管转为 在第二写入周期中的读取电压Vr处截止。

公开(公告)号：US06177847B1

公开(公告)日：2001-01-23

申请号：US09270047

申请日：1999-03-16

申请人： Makoto Nagasue

发明人： Makoto Nagasue

IPC分类号： H03B530

CPC分类号： H03B5/30 ,  H03B5/36

摘要： According to the present invention, there is provided an oscillating circuit comprising: an gate circuit coupled between a first electrical source and a second electrical source, the gate circuit outputting an oscillating signal from an output terminal in response to the standby signal; an switch circuit having an one end and an other end, the one end coupled to the output terminal of the gate circuit and the second terminal, the other end coupled to the first terminal, the switch circuit electrically connecting or disconnecting the first terminal and the second terminal in response to the standby signal.

摘要翻译： 根据本发明，提供了一种振荡电路，包括：门电路，耦合在第一电源和第二电源之间，门电路响应待机信号从输出端输出振荡信号; 具有一端和另一端的开关电路，一端耦合到门电路的输出端和第二端，另一端耦合到第一端，开关电路电连接或断开第一端和 响应待机信号的第二终端。

公开(公告)号：US20050184781A1

公开(公告)日：2005-08-25

申请号：US11058635

申请日：2005-02-16

申请人： Makoto Nagasue

发明人： Makoto Nagasue

IPC分类号： H03K5/04 ,  H03K3/017 ,  H03K5/00 ,  H03K5/156

CPC分类号： H03K5/00006 ,  H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00156

摘要： In a duty adjustment circuit, a clock signal is frequency-divided to ½n by a frequency divider, and then provided to the first frequency doubler among n cascade-connected frequency doublers. In the first frequency doubler, the input clock signal is delayed by a variable delay portion according to a control signal, and the exclusive logical sum of the delayed signal and of the clock signal is taken by a frequency-doubling portion to double the frequency. The average voltage of the frequency-doubled signal is detected by an average value detection portion, this average voltage is compared with a reference voltage by a comparison control portion, and a control signal is fed back to the variable delay portion so as to cause the average voltage to become equal to the reference voltage. In this manner, a clock signal is generated from the last frequency doubler with frequency equal to that of the original clock signal, and with duty ratio adjusted to a desired value.

摘要翻译： 在占空比调整电路中，通过分频器将时钟信号分频为1/2“，然后提供给n个级联连接的倍频器中的第一倍频器。 在第一倍频器中，根据控制信号将输入时钟信号延迟可变延迟部分，并且延迟信号和时钟信号的异或之和由加倍部分取得倍频。 倍频信号的平均电压由平均值检测部分检测，该平均电压通过比较控制部分与参考电压进行比较，并且控制信号反馈到可变延迟部分，以使得 平均电压变为等于参考电压。 以这种方式，从最后的倍频器产生时钟信号，其频率等于原始时钟信号的频率，并且将占空比调整到期望值。

公开(公告)号：US06853240B2

公开(公告)日：2005-02-08

申请号：US10342193

申请日：2003-01-15

申请人： Makoto Nagasue

发明人： Makoto Nagasue

IPC分类号： G06F1/04 ,  H03K19/0175 ,  H03B5/30 ,  H03L7/00

CPC分类号： G06F1/04

摘要： A master clock input circuit with excellent amplification characteristics which generates little noise during mode switching. In a master clock input circuit, the output electric potential of an amplification gate circuit (for example, a NOR gate) is superimposed on a master clock and supplied to the input terminal of an amplification gate circuit. A transmission gate circuit and impedance control gate are provided between the output terminal and input terminal. The transmission gate circuit has low impedance and the impedance control circuit has high impedance. The transmission gate circuit opens and closes the line between the output terminal and input terminal of the amplification gate circuit. Since the impedance of the transmission gate circuit is low, generation of noise is reduced. In addition, since the impedance of the impedance control circuit is high, the amplification factor of the amplification gate circuit becomes higher.

摘要翻译： 具有优异放大特性的主时钟输入电路，在模式切换期间产生很小的噪声。 在主时钟输入电路中，放大门电路（例如，或非门）的输出电位叠加在主时钟上并提供给放大门电路的输入端。 在输出端子和输入端子之间设置传输门电路和阻抗控制门。 传输门电路具有低阻抗，阻抗控制电路具有高阻抗。 传输门电路打开和关闭放大门电路的输出端和输入端之间的线。 由于传输门电路的阻抗低，噪声的产生减少。 此外，由于阻抗控制电路的阻抗高，所以放大门电路的放大系数变高。

公开(公告)号：US06949973B2

公开(公告)日：2005-09-27

申请号：US10766191

申请日：2004-01-29

申请人： Makoto Nagasue

发明人： Makoto Nagasue

IPC分类号： H03F3/68 ,  H03F1/32 ,  H03F3/217 ,  H03K7/08 ,  H03K17/16 ,  H03F1/14

CPC分类号： H03K17/164 ,  H03F1/32 ,  H03F3/2178 ,  H03F2200/114 ,  H03K7/08

摘要： There is provided a signal amplifier capable of restraining the influence of an EMI caused by a distortion of a waveform of an output signal. The signal amplifier comprises an inverter circuit made up of p-channel and n-channel transistors, reference circuits having a circuit configuration corresponding to the inverter circuit and made up of p-channel and n-channel transistors, a selection circuit for selecting the p-channel and n-channel transistors independently with each other with the same combination as the combination of the selection of the p-channel and n-channel transistors in the inverter circuit and the reference circuits, and a selection control circuit for comparing first driving capacity of the p-channel transistor selected in the first reference circuit with second driving capacity of the n-channel transistor selected in the second reference circuit and controlling the selection circuit so as to achieve a balance between the first driving capacity and the second driving capacity on the basis of the result of comparison.

公开(公告)号：US20050068100A1

公开(公告)日：2005-03-31

申请号：US10766191

申请日：2004-01-29

申请人： Makoto Nagasue

发明人： Makoto Nagasue

IPC分类号： H03F3/68 ,  H03F1/32 ,  H03F3/217 ,  H03K7/08 ,  H03K17/16 ,  H03F1/14

CPC分类号： H03K17/164 ,  H03F1/32 ,  H03F3/2178 ,  H03F2200/114 ,  H03K7/08

摘要： There is provided a signal amplifier capable of restraining the influence of an EMI caused by a distortion of a waveform of an output signal. The signal amplifier comprises an inverter circuit made up of p-channel and n-channel transistors, reference circuits having a circuit configuration corresponding to the inverter circuit and made up of p-channel and n-channel transistors, a selection circuit for selecting the p-channel and n-channel transistors independently with each other with the same combination as the combination of the selection of the p-channel and n-channel transistors in the inverter circuit and the reference circuits, and a selection control circuit for comparing first driving capacity of the p-channel transistor selected in the first reference circuit with second driving capacity of the n-channel transistor selected in the second reference circuit and controlling the selection circuit so as to achieve a balance between the first driving capacity and the second driving capacity on the basis of the result of comparison.

摘要翻译： 提供了能够抑制由输出信号的波形的失真引起的EMI的影响的信号放大器。 信号放大器包括由p沟道晶体管和n沟道晶体管构成的反相器电路，参考电路具有对应于反相器电路并由p沟道和n沟道晶体管构成的电路结构，选择电路用于选择p沟道 通道和n沟道晶体管彼此独立地具有与反相器电路中的p沟道和n沟道晶体管的选择和参考电路的组合相同的组合;以及选择控制电路，用于比较第一驱动能力 在第一参考电路中选择的p沟道晶体管的第二驱动电容在第二参考电路中选择的n沟道晶体管的第二驱动电容并且控制选择电路以便实现第一驱动能力和第二驱动能力之间的平衡 比较结果的基础。