公开(公告)号：US20230223465A1

公开(公告)日：2023-07-13

申请号：US18064431

申请日：2022-12-12

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO ,  Hsien-Hsin LIN

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66439

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a fin structure and an epitaxial source/drain structure. The substrate includes a substrate layer and an insulator layer on the substrate layer. The fin structure is formed over the substrate, wherein the fin structure includes a gate structure and channel layers wrapped by the gate structure. The epitaxial source/drain structure is connected to the channel layers, wherein a bottom portion of the epitaxial source/drain structure is in contact with the insulator layer of the substrate.

公开(公告)号：US20230223276A1

公开(公告)日：2023-07-13

申请号：US18067886

申请日：2022-12-19

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO ,  Hsien-Hsin LIN

IPC: H01L21/48 ,  H01L21/02 ,  H01L21/04 ,  H01L21/762 ,  H01L21/768 ,  H01L29/08

CPC classification number: H01L21/481 ,  H01L21/02293 ,  H01L21/045 ,  H01L21/76243 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/02362 ,  H01L29/0847

Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulator layer, first and second field-effect transistor devices, an isolation field-effect transistor device, front-side gate and back-side gate contacts. Each of the first and second field-effect transistor devices and the isolation field-effect transistor device includes a fin structure and first and second epitaxial source/drain structures. The fin structure includes channel layers and a gate structure that is wrapped around the channel layers. The first and second epitaxial source/drain structures are connected to opposite sides of the channel layers. The isolation field-effect transistor device is kept in the off-state. The front-side gate contact is formed on the first field-effect transistor device and electrically connected to the gate structure of the first field-effect transistor device. The back-side gate contact is formed passing through the insulator layer and electrically connected to the gate structure of the isolation field-effect transistor device.

公开(公告)号：US20210050315A1

公开(公告)日：2021-02-18

申请号：US16928089

申请日：2020-07-14

Applicant: MEDIATEK Inc.

Inventor： Po-Chao TSAO ,  Yu-Hua HUANG

IPC: H01L23/00

Abstract: A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

公开(公告)号：US20250098283A1

公开(公告)日：2025-03-20

申请号：US18971358

申请日：2024-12-06

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO

IPC: H01L21/8234 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a substrate, a first well region on the substrate, a shallow trench isolation (STI) region over the first well region, and a first transistor. The first transistor includes a first fin formed on the first well region, a first gate electrode formed on the first fin, and a first doping region formed on the first fin. The semiconductor structure further includes a first power rail on the first well region and in the STI region and a first source/drain contact over the first doping region and the first power rail to electrically connect the first doping region to the first power rail. A bottom surface of first source/drain contact is in direct contact with the STI region.

公开(公告)号：US20230128880A1

公开(公告)日：2023-04-27

申请号：US17936553

申请日：2022-09-29

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/398

Abstract: A semiconductor device includes a substrate, a first cell and a second cell on the substrate. The first cell includes a first diffusion region in the substrate, a first gate structure over the first diffusion region, and a first contact over the first diffusion region. The first contact is disposed on one side of the first gate structure. The second cell that abuts the first cell includes a second diffusion region in the substrate, a second gate structure over the second diffusion region and a second contact over the second diffusion region. The second contact that is positioned on one side of the second gate structure is adjacent to the first contact of the first cell. The first contact and the second contact are equipotential when the semiconductor device is in operation. The second diffusion region and the first diffusion region form a continuous diffusion region.

公开(公告)号：US20230080688A1

公开(公告)日：2023-03-16

申请号：US18053944

申请日：2022-11-09

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.

公开(公告)号：US20210313317A1

公开(公告)日：2021-10-07

申请号：US17134694

申请日：2020-12-28

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.

公开(公告)号：US20190080969A1

公开(公告)日：2019-03-14

申请号：US16059196

申请日：2018-08-09

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.