公开(公告)号：US20230223465A1

公开(公告)日：2023-07-13

申请号：US18064431

申请日：2022-12-12

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO ,  Hsien-Hsin LIN

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66439

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a fin structure and an epitaxial source/drain structure. The substrate includes a substrate layer and an insulator layer on the substrate layer. The fin structure is formed over the substrate, wherein the fin structure includes a gate structure and channel layers wrapped by the gate structure. The epitaxial source/drain structure is connected to the channel layers, wherein a bottom portion of the epitaxial source/drain structure is in contact with the insulator layer of the substrate.

公开(公告)号：US20180138104A1

公开(公告)日：2018-05-17

申请号：US15800611

申请日：2017-11-01

Applicant: MEDIATEK INC.

Inventor： Hsien-Hsin LIN ,  Ming-Tzong YANG ,  Wen-Kai WAN

IPC: H01L23/367 ,  H01L29/78 ,  H01L23/535 ,  H01L23/528

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

公开(公告)号：US20230223276A1

公开(公告)日：2023-07-13

申请号：US18067886

申请日：2022-12-19

Applicant: MEDIATEK INC.

Inventor： Po-Chao TSAO ,  Hsien-Hsin LIN

IPC: H01L21/48 ,  H01L21/02 ,  H01L21/04 ,  H01L21/762 ,  H01L21/768 ,  H01L29/08

CPC classification number: H01L21/481 ,  H01L21/02293 ,  H01L21/045 ,  H01L21/76243 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/02362 ,  H01L29/0847

Abstract: A semiconductor structure is provided. The semiconductor structure includes an insulator layer, first and second field-effect transistor devices, an isolation field-effect transistor device, front-side gate and back-side gate contacts. Each of the first and second field-effect transistor devices and the isolation field-effect transistor device includes a fin structure and first and second epitaxial source/drain structures. The fin structure includes channel layers and a gate structure that is wrapped around the channel layers. The first and second epitaxial source/drain structures are connected to opposite sides of the channel layers. The isolation field-effect transistor device is kept in the off-state. The front-side gate contact is formed on the first field-effect transistor device and electrically connected to the gate structure of the first field-effect transistor device. The back-side gate contact is formed passing through the insulator layer and electrically connected to the gate structure of the isolation field-effect transistor device.

公开(公告)号：US20230154824A1

公开(公告)日：2023-05-18

申请号：US18155322

申请日：2023-01-17

Applicant: Chee-Wee LIU ,  MEDIATEK INC.

Inventor： Ming-Tzong YANG ,  Hsien-Hsin LIN ,  Wen-Kai WAN ,  Chia-Che CHUNG ,  Chee-Wee LIU

IPC: H01L23/373 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/373 ,  H01L21/768 ,  H01L29/785 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm−1K−1and 1200 Wm−1K−1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.