公开(公告)号：US12087664B2

公开(公告)日：2024-09-10

申请号：US18129061

申请日：2023-03-30

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Sheng-Liang Kuo ,  Bo-Jiun Yang

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/16

CPC classification number: H01L23/473 ,  H01L23/16 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.

公开(公告)号：US20230396250A1

公开(公告)日：2023-12-07

申请号：US18204374

申请日：2023-05-31

Applicant: MEDIATEK INC.

Inventor： Chen-Han Tsai ,  Chia-Hao Hsu ,  Zhi-Gang Zeng ,  Cheng-Tang Chen

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0944

CPC classification number: H03K19/0016 ,  H03K19/018514 ,  H03K19/0944

Abstract: The present invention provides a clock buffer, wherein the clock buffer receives an input signal at a first node and generate an output signal at a second node. The clock buffer includes a P-type transistor, a first N-type transistor, a resistor, a transistor and a switch. A source electrode, a gate electrode and a drain electrode of the P-type transistor are coupled to a supply voltage, the first node, and the second node, respectively. A gate electrode, a drain electrode and a source electrode of the first N-type transistor are coupled to the first node, the second node and a third node, respectively. The resistor is coupled between the first node and the second node. The transistor is coupled between the first N-type transistor and a ground voltage. The switch is configured to selectively connect the third node to the ground voltage.

公开(公告)号：US11227846B2

公开(公告)日：2022-01-18

申请号：US16742850

申请日：2020-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US20200301860A1

公开(公告)日：2020-09-24

申请号：US16810031

申请日：2020-03-05

Applicant: MediaTek Inc.

Inventor： Chia-Hao Hsu ,  Sen-Yu Cheng ,  Yan-Ting Chen ,  Po-Kai Chi

IPC: G06F13/24 ,  G06F1/3293

Abstract: A multi-processor system handles interrupts using a power and performance status of each processor and a usage scenario of each processor. The power and performance status is indicated by factors that affect power consumption and processor performance. The system identifies one of the processors for handling an interrupt based on a weighted combination of the factors. Each factor is weighted based on a usage scenario for which the interrupt was generated. The system then dispatches the interrupt to the identified one of the processors.

公开(公告)号：US20200243462A1

公开(公告)日：2020-07-30

申请号：US16742850

申请日：2020-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q1/02

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US09977699B2

公开(公告)日：2018-05-22

申请号：US14936686

申请日：2015-11-10

Applicant: MediaTek Inc.

Inventor： Jia-Ming Chen ,  Hung-Lin Chou ,  Ya-Ting Chang ,  Shih-Yen Chiu ,  Chia-Hao Hsu ,  Yu-Ming Lin ,  Wan-Ching Huang ,  Jen-Chieh Yang ,  Pi-Cheng Hsiao

IPC: G06F9/46 ,  G06F9/50 ,  G06F1/32

CPC classification number: G06F9/5094 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/329 ,  G06F2209/505 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

公开(公告)号：US11705413B2

公开(公告)日：2023-07-18

申请号：US17549901

申请日：2021-12-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L23/3672 ,  H01L23/3733 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01Q1/02 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/18161

Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US20220102297A1

公开(公告)日：2022-03-31

申请号：US17549901

申请日：2021-12-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US20200243464A1

公开(公告)日：2020-07-30

申请号：US16802576

申请日：2020-02-27

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01Q1/02 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/373

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US12300573B2

公开(公告)日：2025-05-13

申请号：US17700571

申请日：2022-03-22

Applicant: MEDIATEK Inc.

Inventor： Bo-Jiun Yang ,  Wen-Sung Hsu ,  Tai-Yu Chen ,  Sheng-Liang Kuo ,  Chia-Hao Hsu

IPC: H01L23/42 ,  H01L21/48 ,  H01L23/00 ,  H01L23/427 ,  H01L23/433

Abstract: A semiconductor device includes a substrate, an electronic component, a cover and a liquid metal. The electronic component is disposed on the substrate. The cover is disposed on the substrate and covers the electronic component. The liquid metal is formed between the cover and the electronic component.