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公开(公告)号:US20230401420A1
公开(公告)日:2023-12-14
申请号:US17838240
申请日:2022-06-12
Applicant: MediaTek Inc.
Inventor: Chih-Wen Goo , Pei-Kuei Tsung , Chih-Wei Chen , Mingen Shih , Shu-Hsin Chang , Po-Hua Huang , Ping-Yuan Tsai , Shih-Wei Hsieh , You Yu Nian
CPC classification number: G06N3/04 , G06F9/3001
Abstract: A system receives a neural network model that includes asymmetric operations. Each asymmetric operation includes one or more fixed-point operands that are asymmetrically-quantized from corresponding floating-point operands. The system compiles a given asymmetric operation of the neural network model into a symmetric operation that includes a combined bias value. A compiler computes the combined bias value is a constant by merging at least zero points of input and output of the given asymmetric operation. The system then generates a symmetric neural network model including the symmetric operation for inference hardware to execute in fixed-point arithmetic.
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公开(公告)号:US20210287339A1
公开(公告)日:2021-09-16
申请号:US17196957
申请日:2021-03-09
Applicant: MEDIATEK INC.
Inventor: Ming-En Shih , Yu-Cheng Tseng , Kuo-Chen Huang , Pei-Kuei Tsung , Hsin-Min Peng , Ping-Yuan Tsai , Kuo-Chiang Lo , Chun-Hsien Wu , Chih-Wei Chen , Cheng-Lung Jen
Abstract: An image processing apparatus includes a super-resolution (SR) circuit and a resizer circuit. The SR circuit performs an SR operation upon a first image to generate a second image, wherein a resolution of the second image is not lower than a resolution of the first image, and the SR operation is based, at least in part, on one or more artificial intelligence (AI) models. The resizer circuit performs a resize operation upon the second image to generate a third image, wherein a resolution of the third image is not lower than the resolution of the second image, and no AI model is involved in the resize operation.
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公开(公告)号:US20250077282A1
公开(公告)日:2025-03-06
申请号:US18820342
申请日:2024-08-30
Applicant: MEDIATEK INC.
Inventor: Ming-Hung Lin , Ming-En Shih , Shih-Wei Hsieh , Ping-Yuan Tsai , You-Yu Nian , Pei-Kuei Tsung , Jen-Wei Liang , Shu-Hsin Chang , En-Jui Chang , Chih-Wei Chen , Po-Hua Huang , Chung-Lun Huang
Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.
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公开(公告)号:US20210287338A1
公开(公告)日:2021-09-16
申请号:US17118162
申请日:2020-12-10
Applicant: MediaTek Inc.
Inventor: Ming-En Shih , Ping-Yuan Tsai , Yu-Cheng Tseng , Kuo-Chen Huang , Kuo-Chiang Lo , Hsin-Min Peng , Chun Hsien Wu , Pei-Kuei Tsung , Tung-Chien Chen , Yao-Sheng Wang , Cheng Lung Jen , Chih-Wei Chen , Chih-Wen Goo , Yu-Sheng Lin , Tsu Jui Hsu
Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligent (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.
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公开(公告)号:US20250077180A1
公开(公告)日:2025-03-06
申请号:US18820312
申请日:2024-08-30
Applicant: MEDIATEK INC.
Inventor: Ming-Hung Lin , Ming-En Shih , Shih-Wei Hsieh , Ping-Yuan Tsai , You-Yu Nian , Pei-Kuei Tsung , Jen-Wei Liang , Shu-Hsin Chang , En-Jui Chang , Chih-Wei Chen , Po-Hua Huang , Chung-Lun Huang
Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.
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公开(公告)号:US12062151B2
公开(公告)日:2024-08-13
申请号:US17118162
申请日:2020-12-10
Applicant: MediaTek Inc.
Inventor: Ming-En Shih , Ping-Yuan Tsai , Yu-Cheng Tseng , Kuo-Chen Huang , Kuo-Chiang Lo , Hsin-Min Peng , Chun Hsien Wu , Pei-Kuei Tsung , Tung-Chien Chen , Yao-Sheng Wang , Cheng Lung Jen , Chih-Wei Chen , Chih-Wen Goo , Yu-Sheng Lin , Tsu Jui Hsu
IPC: G06T3/4053 , G06F13/00 , G06N3/04 , G06N3/08 , G06T3/4046 , G06T5/70 , G06T7/00 , G09G5/391 , H01L21/033 , H04N9/31
CPC classification number: G06T3/4053 , G06F13/00 , G06N3/04 , G06N3/08 , G06T3/4046 , G06T5/70 , G06T7/0002 , G09G5/391 , H01L21/0338 , H04N9/3188 , G06T2207/20081 , G06T2207/20084 , G06T2207/30168
Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.
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