公开(公告)号：US20240177019A1

公开(公告)日：2024-05-30

申请号：US18323908

申请日：2023-05-25

Applicant: MEDIATEK INC.

Inventor： Chieh-Fang TENG ,  En-Jui Chang ,  Chih Chung CHENG

IPC: G06N3/10 ,  G06N3/063

CPC classification number: G06N3/10 ,  G06N3/063

Abstract: Aspects of the present disclosure provide an apparatus. For example, the apparatus can include a compiler configured to compile a neural network (NN) model to generate a plurality of operations/threads and determine whether each of the operations/threads is compute bound or memory bound, and a memory coupled to the compiler and configured to store the operations/threads. The apparatus can also include a thread scheduler coupled to the memory and configured to schedule the operations/threads of the NN model. The apparatus can also include a multi-engine processing unit that includes a plurality of compute units (CUs), and an executor coupled between the thread scheduler and the multi-engine processing unit. The executor can be configured to allocate the operations/threads of the NN model and activate a number of the CUs of the multi-engine processing unit for each of the operations/threads based on whether the operation/thread is compute bound or memory bound.

公开(公告)号：US20250077282A1

公开(公告)日：2025-03-06

申请号：US18820342

申请日：2024-08-30

Applicant: MEDIATEK INC.

Inventor： Ming-Hung Lin ,  Ming-En Shih ,  Shih-Wei Hsieh ,  Ping-Yuan Tsai ,  You-Yu Nian ,  Pei-Kuei Tsung ,  Jen-Wei Liang ,  Shu-Hsin Chang ,  En-Jui Chang ,  Chih-Wei Chen ,  Po-Hua Huang ,  Chung-Lun Huang

IPC: G06F9/50 ,  G06F17/15

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

公开(公告)号：US20250077180A1

公开(公告)日：2025-03-06

申请号：US18820312

申请日：2024-08-30

Applicant: MEDIATEK INC.

Inventor： Ming-Hung Lin ,  Ming-En Shih ,  Shih-Wei Hsieh ,  Ping-Yuan Tsai ,  You-Yu Nian ,  Pei-Kuei Tsung ,  Jen-Wei Liang ,  Shu-Hsin Chang ,  En-Jui Chang ,  Chih-Wei Chen ,  Po-Hua Huang ,  Chung-Lun Huang

IPC: G06F7/505 ,  G06F7/57

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

公开(公告)号：US20240333639A1

公开(公告)日：2024-10-03

申请号：US18128215

申请日：2023-03-29

Applicant: MEDIATEK INC.

Inventor： En-Jui Chang ,  Chih-Chung Cheng

IPC: H04L45/42 ,  H04L41/16 ,  H04L45/02

CPC classification number: H04L45/42 ,  H04L41/16 ,  H04L45/02

Abstract: A multi-stage interconnection network includes an M-stage plane routing network and an N-stage destination routing network. The M-stage plane routing network routes a data packet received by an input port of the multi-stage interconnection network to a switch plane according to an M-bit entry selected from a plane encoding table, wherein M bits of the M-bit entry control M stages of the M-stage plane routing network, respectively. The N-stage destination routing network routes the data packet from the switch plane to at least one output port of the multi-stage interconnection network according to at least one N-bit entry selected from a destination encoding table, wherein N bits of each of the at least one N-bit entry control N stages of the N-stage destination routing network, respectively. The multi-stage interconnection network employs a non-blocking network topology.